Low-Latency Modular Multiplication Circuits Using Shared Carry-Outs
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Solution Overview
Problem
Integrated circuit devices, particularly programmable logic devices like FPGAs, face high latency and excessive circuit area usage in performing modular multiplication operations, which is undesirable for applications such as machine learning, artificial intelligence, and cryptocurrency.
Innovation Solution
The implementation of multiplier circuitry that reduces latency and circuit area by decomposing large values into subproducts, using adder trees with shared carry-out values and ternary adders to perform modular multiplication efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If conventional modular multiplication circuitry is used, then the operation can be performed, but the latency is undesirably high
Solution Approach 1:
The patent segments the modular multiplication operation into distinct phases: a first adder tree performs initial partial product summations, while a second adder tree performs final summations. This segmentation allows parallel processing of different computational stages, reducing overall latency compared to sequential conventional approaches.
Solution Approach 2:
The first adder tree performs preliminary computations by calculating partial product summations before the final reduction step. This preliminary action prepares intermediate results that can be efficiently combined in the second adder tree, optimizing the overall computation pipeline and reducing critical path latency.
2Area of stationary object
If conventional modular multiplication circuitry is used, then the operation can be performed, but the circuit area occupied is undesirable
Solution Approach 1:
The computational task is divided between two adder trees, each handling specific portions of the modular multiplication. This segmentation allows for more efficient resource utilization and reduces the total circuit area compared to a single monolithic multiplier design, while maintaining full computational capability.
Solution Approach 2:
The multipliers within the adder trees are designed to be universal components that can handle different operand sizes and configurations. This multi-functionality reduces the need for specialized circuitry for each operation type, thereby reducing overall circuit area while maintaining versatility.
3Loss of time
If conventional adder trees are used, then summation can be performed, but carry propagation causes increased latency
Solution Approach 1:
The patent divides the summation process into two separate adder trees, where the first adder tree handles initial partial product summations and the second adder tree handles final summations. This segmentation breaks the long carry propagation chain into shorter segments, reducing the overall carry propagation time and increasing summation speed.
Data Source
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AI summary
An integrated circuit device includes multiplier circuitry configured to determine a plurality of columns of subproducts by multiplying a plurality of values. Each column of the plurality of columns includes one or more subproducts of a plurality of subproducts. The integrated circuit device also includes adder circuitry configured to determine a plurality of sums, each sum being a sum of one column of the plurality of columns. A first portion of the adder circuitry associated with a first column of the plurality of columns is configured to receive a first value and second value that are associated with the first column and a third value associated with a second column of the plurality of columns that differs from the first column. The third value is a carry-out value generated by a second portion of the adder circuitry associated with the second column of the plurality of columns.