Low Latency Re-timer for USB Type-C Spread Spectrum Clocking
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Solution Overview
Problem
Current re-timers in the USB Type-C ecosystem suffer from high latency due to significant frequency gaps between receiver and transmitter clocks, leading to quality of service issues and potential functional failures.
Innovation Solution
Implementing a tracking loop in the Spread Spectrum Clocking waveform generator at the transmitter side to align the dynamic frequency modulation of the transmitter clock with the receiver clock, reducing the frequency gap and thereby minimizing FIFO latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If a tracking loop is implemented to align transmitter and receiver clocks, then latency is reduced, but device complexity increases
Solution Approach 1:
A tracking loop is implemented that continuously monitors the frequency gap between receiver and transmitter clocks and dynamically adjusts the transmitter clock frequency to minimize the gap. This feedback mechanism reduces FIFO latency by keeping the clocks synchronized, thereby resolving the technical contradiction between reduced latency and increased device complexity.
Solution Approach 2:
The transmitter clock frequency is dynamically adjusted based on the received clock frequency to minimize the frequency gap. By changing the frequency parameter of the transmitter clock in real-time, the system reduces the latency caused by large frequency differences while managing the complexity through controlled parameter modification.
2Loss of time
If the frequency gap between receiver and transmitter clocks is reduced, then FIFO latency is minimized, but the device complexity increases due to the tracking loop
Solution Approach 1:
The tracking loop continuously monitors the frequency gap between receiver and transmitter clocks and dynamically adjusts the transmitter clock frequency to minimize the gap. This feedback mechanism reduces FIFO latency by keeping the clocks synchronized, thereby resolving the technical contradiction between reduced latency and increased device complexity.
Solution Approach 2:
The system transitions from static clock frequencies to dynamic frequency adjustment. The transmitter clock frequency is continuously adapted based on the received clock frequency, allowing the system to minimize FIFO latency through real-time frequency matching while managing complexity through controlled dynamic behavior.
Data Source
AI summary
Described is a low latency re-timer for systems supporting spread spectrum clocking. The re-timer comprises: a first clock frequency estimator to estimate a frequency of a receive clock (RX CLK) and to provide a first timestamp associated with a first clock that underwent spread spectrum; a second clock frequency estimator to estimate a frequency of a transmit clock (TX CLK) and to provide a second timestamp associated with a second clock that underwent spread spectrum; and a comparator to compare the first timestamp with the second timestamp.