Low-Leakage Voltage Level Shifter for Power-Saving IC Modes
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Solution Overview
Problem
Conventional voltage level shifters introduce stray current during power saving modes in integrated circuits, defeating the purpose of reduced power consumption and causing unintentional active current flow.
Innovation Solution
A modified voltage level shifting circuit with high voltage PMOS transistors and NMOS switching devices that are turned off during power saving modes to block leakage paths, utilizing a voltage detection circuit to control the switching devices and prevent current flow between external high voltage and internal low voltage levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conventional voltage level shifters are used to shift external high voltage signals to internal low voltage signals, then voltage level conversion is achieved, but stray current flows during power saving modes defeating the purpose of reduced power consumption
Solution Approach 1:
The patent applies dynamics by making the voltage level shifter operational state changeable through the power saving mode control signal. The circuit dynamically transitions between active and inactive states, where high voltage transistors are turned off during power saving modes to eliminate leakage paths while remaining functional during normal operation. This dynamic state change allows the circuit to adapt its power consumption characteristics based on operational requirements.
Solution Approach 2:
The patent uses control signals (POCH and POCHB) as intermediaries to manage the operation of the voltage level shifter. These control signals coordinate the switching of high voltage transistors based on the power saving mode status, acting as a mediator between the power management system and the voltage level shifting function. The intermediary control mechanism ensures that leakage prevention is activated only when appropriate without disrupting normal voltage conversion operations.
2Reliability
If high voltage transistors are kept on to maintain voltage level shifting capability, then voltage conversion function is preserved, but unintentional active current flows during power saving modes
Solution Approach 1:
The circuit implements dynamic control where high voltage transistors switch between on and off states based on operational mode. During normal operation, transistors remain on to enable voltage level shifting. During power saving modes, transistors are turned off to eliminate active current flow. This dynamic behavior allows the circuit to maintain reliability when needed while eliminating energy loss during power saving operations.
Solution Approach 2:
The patent employs feedback through voltage detection circuits that monitor the power saving mode status and generate appropriate control signals. The detection circuit provides feedback about the operational state to the voltage level shifter, enabling the transistors to respond appropriately. This feedback mechanism ensures that the voltage shifting function is maintained during normal operation while preventing active current flow during power saving modes.
3Use of energy by moving object
If voltage level shifter operates in power saving mode with lowered internal voltage, then power consumption is reduced, but leakage paths remain active causing current flow
Solution Approach 1:
The patent extracts and removes the leakage paths from the active circuit by turning off high voltage transistors during power saving modes. This extraction of potentially problematic conduction paths eliminates the source of leakage current while maintaining the circuit's ability to restore full functionality when needed. The removed leakage paths are effectively isolated from the active circuit operation.
Solution Approach 2:
The circuit dynamically adjusts its conduction characteristics by switching high voltage transistors off during power saving modes. This dynamic state change eliminates leakage paths when the internal voltage is lowered, while preserving the capability to restore full voltage conversion functionality when the circuit returns to normal operation. The dynamic adaptation allows the circuit to optimize between power consumption and functional readiness.
Data Source
AI summary
A voltage level shifting circuit for an integrated circuit system having an internal low voltage power supply (VCCL) and an external high voltage power supply (VCCH) is disclosed, the voltage level shifting circuit comprises a pair of cross coupled PMOS transistors connected to the VCCH, a NMOS transistor with a source connected to a ground (VSS) and a gate connected to a first signal swinging between the VCCL and the VSS, and a switching device coupled between a drain of one of the pair of PMOS transistors and a drain of the NMOS transistor, wherein the pair of PMOS transistors are high voltage transistors and the switching device is off when the VCCL is below a predetermined voltage level, and the switching device is on when the VCCL is above the predetermined voltage level.