Low-Leakage Row Decoder With Clocked Power Gating
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Solution Overview
Problem
Memory circuits, such as SRAM circuits, face high leakage power consumption in peripheral circuitry even during normal active mode, necessitating the use of light sleep modes that require additional components and power-down mechanisms.
Innovation Solution
A low-leakage row decoder structure with clocked power gating, featuring first and second logic gates connected to supply voltage rails through switches controlled by clock signal-dependent control signals, eliminating the need for light sleep mode operations and additional components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If light sleep mode is implemented to minimize leakage power consumption, then leakage power consumption is reduced, but device complexity increases due to additional components and power-down mechanisms
Solution Approach 1:
The patent applies dynamics by making the power supply rails dynamic rather than static. The first and second voltage rails are selectively connected to the logic gates through switches controlled by clock signals, allowing the circuit to transition between powered and unpowered states dynamically. This eliminates the need for separate light sleep mode components while still achieving low leakage power consumption during idle periods.
Solution Approach 2:
The patent changes the power supply parameter from a constant voltage rail to a dynamically controlled voltage rail. By using clock signal-dependent control signals to switch the connection between voltage rails and logic gates, the system can change its power consumption state without additional light sleep mode hardware, thus reducing device complexity while maintaining low leakage power consumption.
2Device complexity
If conventional row decoder structure is used, then device complexity is low, but leakage power consumption remains high during normal active mode
Solution Approach 1:
The patent segments the power supply circuitry by dividing the voltage rails into first and second voltage rails that can be independently controlled. Each voltage rail is connected to specific logic gates through switches, allowing selective powering of different circuit segments. This segmentation enables low leakage power consumption during active mode by powering only the necessary segments rather than the entire decoder structure.
3Loss of energy
If light sleep mode is used, then leakage power consumption is minimized during idle time, but the need for additional hardware components increases
Solution Approach 1:
The patent makes the clock signal-dependent control signals serve multiple functions: they control the switches to power the logic gates during active mode and simultaneously enable the leakage current paths during idle mode. This multi-functionality eliminates the need for separate light sleep mode hardware components, as the same control mechanism achieves both active mode operation and idle mode power savings.
Data Source
AI summary
Disclosed are embodiments of a low-leakage row decoder and a memory circuit incorporating the row decoder. The row decoder includes wordline driver circuitry including first devices (pre-drivers) and second devices (wordline drivers). Each second device is connected in series between a first device and a wordline for a row in a memory array. The first devices can be directly connected to a positive supply voltage rail and connected to a ground rail through a footer. The second devices can be connected to the positive supply voltage rail through a header and directly connected to the ground rail. The on/off states of the header and footer are controlled by clock signal-dependent control signals so that they are either concurrently on or off. With this configuration, leakage power consumption of the wordline driver circuitry is minimized while the memory structures as idle and also while it operates in a normal active mode.