Low-Loss Semiconductor Substrate for III-V RF Epitaxy
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Solution Overview
Problem
The integration of III-V materials on silicon substrates for RF applications is hindered by the formation of parasitic surface conductive layers due to resistivity reduction caused by III-V material diffusion, leading to RF losses and harmonic generation, which existing solutions like trap-rich layers do not adequately address.
Innovation Solution
A substrate structure comprising a base substrate, a dielectric layer, a trap-rich layer, and a crystalline semiconductor layer, with the trap-rich layer positioned between the dielectric and crystalline layers to neutralize parasitic surface conductive layers, allowing for epitaxial growth of III-V materials with reduced RF energy loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If III-V materials are grown on high resistivity silicon substrate, then RF device performance is improved, but parasitic surface conductive layers form causing RF losses
Solution Approach 1:
An intermediate layer stack comprising a dielectric layer and a trap-rich layer is introduced between the III-V semiconductor layer and the silicon substrate. The trap-rich layer contains charge traps that neutralize positive charges in the silicon substrate, preventing the formation of parasitic surface conductive layers, while the dielectric layer provides electrical isolation. This intermediary structure eliminates RF losses without compromising device performance.
Solution Approach 2:
The trap-rich layer is positioned to preemptively counteract the formation of parasitic surface conductive layers by neutralizing positive charges in the silicon substrate before they can create harmful conductive paths. This preliminary charge neutralization prevents the adverse effect rather than addressing it after formation.
2Adaptability or versatility
If III-V material diffusion occurs in Si during epitaxial growth, then material integration is achieved, but resistivity of Si layer decreases forming PSC layers
Solution Approach 1:
The dielectric layer and trap-rich layer stack acts as a physical and electrical intermediary between the III-V material and silicon substrate. This intermediate structure allows epitaxial growth to proceed while preventing excessive diffusion that would compromise silicon resistivity, maintaining manufacturing precision through controlled interaction.
Solution Approach 2:
The harmful diffusion effect is extracted and contained within the intermediate layer structure. The trap-rich layer specifically captures diffusing species and neutralizes their harmful effects, separating the beneficial integration function from the harmful resistivity reduction.
3Reliability
If existing trap-rich layer solutions are applied under oxide layer, then free charges are neutralized, but PSC layers at oxide/Si interface are not mitigated
Solution Approach 1:
The solution moves from a single-layer trap-rich structure to a multi-dimensional layer stack comprising both a dielectric layer and a trap-rich layer in sequence. This dimensional expansion of the intermediate structure allows simultaneous addressing of multiple interface problems: the trap-rich layer neutralizes charges while the dielectric layer isolates the PSC effect at the oxide/Si interface.
Solution Approach 2:
The intermediate structure is segmented into two functional layers: the dielectric layer provides electrical isolation and physical separation, while the trap-rich layer provides charge neutralization. This segmentation allows each layer to specialize in one function, effectively mitigating both types of PSC layers simultaneously.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed substrate structure effectively neutralizes parasitic surface conductive layers, resulting in a low-loss substrate suitable for RF devices, particularly beneficial for III-V material-based RF circuits and devices.
Implementation Method 1
The trap-rich layer, between the dielectric layer and the crystalline semiconductor layer, enables the neutralization of a parasitic surface conductive layer at the interface between the crystalline layer and the compound layer or layers, and of an additional PSC layer caused by a direct contact between the crystalline layer and the dielectric layer
Implementation Method 2
The substrate of the invention is suitable for epitaxially growing on the surface of the crystalline semiconductor layer one or more layers of a compound semiconductor
Implementation Method 3
the resistivity of the Si layer decreases as a consequence of III-V material diffusing in the Si during the high-temperature epitaxial growth of the material
Data Source
Figure 1a~1b
Figure 2a~2c
Figure 2d
AI summary
A substrate (1) according to the invention comprises a base substrate (2), a dielectric layer (3), a trap-rich layer (4) on the dielectric layer, and a crystalline semiconductor layer (5) on the trap-rich layer. The dielectric layer (3) may be a stack of multiple dielectric sublayers formed of the same dielectric material or formed of two or more different dielectric materials. The substrate of the invention is suitable for epitaxially growing on the surface of the crystalline semiconductor layer (5) one or more layers (6,7,8) of a compound semiconductor. The preferred application is the growth of a stack of layers of III-V material with one or more upper layers of the stack being suitable for processing in and/or on said layers a number of semiconductor devices such as transistors or diodes. The position of the trap-rich layer (4), between the dielectric layer (3) and the crystalline semiconductor layer (5), enables the neutralization of a parasitic surface conductive layer at the interface between the crystalline layer (5) and the compound layer or layers (6,7,8), and of an additional PSC layer caused by a direct contact between the crystalline layer (5) and the dielectric layer (3). The invention is equally related to methods for producing the substrate of the invention.