Low Noise Memory Array With Trench Isolation
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Solution Overview
Problem
Memory arrays face increased noise issues due to parasitic capacitance, which degrades signal quality and can lead to read errors, especially as feature sizes decrease, in both folded and cross point configurations.
Innovation Solution
The implementation of a memory array architecture with trench isolation regions and separate semiconductor regions, along with a word line drive circuit that selectively activates memory cells to minimize noise by maintaining bit lines at a stable precharge voltage, thereby reducing parasitic capacitance effects and enhancing signal-to-noise ratio.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If feature sizes are decreased to increase memory density, then the number of memory cells increases, but parasitic capacitance increases and signal quality degrades
Solution Approach 1:
The bit line is divided into multiple segments with separate word line controls. Each segment can be independently activated, allowing the memory array to be divided into smaller active regions. This segmentation reduces the parasitic capacitance coupling between adjacent signal lines within each segment while maintaining high memory density through efficient space utilization.
Solution Approach 2:
Reference bit lines are introduced as intermediary elements between signal bit lines. These reference bit lines are controlled by separate word lines and serve to cancel out parasitic capacitance effects through differential signaling. The reference bit lines act as mediators that compensate for noise coupling from adjacent active bit lines, thereby improving signal quality without requiring larger feature sizes.
2Area of stationary object
If adjacent bit lines are placed close together to increase memory density, then area efficiency improves, but noise coupling through parasitic capacitance increases
Solution Approach 1:
The memory array is segmented into multiple blocks, each with its own set of word lines and bit line segments. This segmentation allows adjacent bit lines to be placed close together for area efficiency while limiting noise coupling to within smaller segments. The separate word line controls for each segment enable independent activation, reducing cross-segment noise interference.
Solution Approach 2:
Reference bit lines serve as intermediary elements that are positioned between signal bit lines. These reference bit lines are controlled by separate word lines and provide a noise reference that cancels out parasitic capacitance effects from adjacent active bit lines. This intermediary structure enables close spacing of bit lines while maintaining signal integrity through differential sensing.
3Speed
If all bit lines are activated simultaneously to maximize memory access speed, then access time decreases, but noise from signal transitions on adjacent lines increases
Solution Approach 1:
Word lines are divided into multiple independently controllable segments, allowing selective activation of only the necessary memory cell rows. This segmentation enables fast access to specific data regions without activating all bit lines simultaneously, thereby reducing noise from unnecessary signal transitions on adjacent inactive bit lines while maintaining high access speed for the active segments.
Solution Approach 2:
Bit lines are precharged to a reference voltage level before memory access operations. This preliminary action ensures that when word lines are activated, the bit lines are already in the correct initial state, reducing the magnitude and duration of signal transitions. This precharging minimizes parasitic capacitance effects and noise coupling between adjacent bit lines during the actual memory access, thereby improving signal quality without sacrificing access speed.
Data Source
AI summary
A circuit compatible with dynamic random access memories (DRAM) and static random access memories (SRAM) is disclosed. The circuit includes a substrate having a first conductivity type. A trench isolation region (850,852) is formed in the substrate. The trench isolation region has sides and a bottom formed below a face of the substrate. A first semiconductor region having a second conductivity type (868) is formed at the bottom of the trench isolation region. A second semiconductor region having the second conductivity type (870) is formed separately from the first semiconductor region adjacent a first side of trench isolation region and in conductive contact with the first semiconductor region.