Low Parasitic Capacitor Array With Vertical Stacking
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Solution Overview
Problem
Capacitor arrays in analog-to-digital converters face challenges in maintaining ratio matching due to parasitic capacitance and process variations, leading to differential non-linearity and integral non-linearity issues, which are exacerbated by the increasing size of capacitors and high integration levels.
Innovation Solution
A capacitor array design featuring vertically stacked first metal plates, a horizontally stacked second metal plate coupling one end of each first metal plate, and vertically stacked third metal plates between pairs of first metal plates, minimizing parasitic capacitance and process variation effects by ensuring equal capacitance between top and bottom plates without the need for dummy capacitors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If capacitor size is increased to maintain capacitance value, then capacitance value is improved, but parasitic capacitance increases
Solution Approach 1:
The patent transitions from planar capacitor layout to three-dimensional vertically stacked configuration. Multiple capacitor plates are stacked in the vertical dimension (Z-axis) with alternating top and bottom plates, allowing increased capacitance value without increasing parasitic capacitance proportionally. The vertical stacking enables higher capacitance density while maintaining controlled parasitic effects through the structured arrangement of conductive plates and dielectric layers.
2Productivity
If integration level is increased, then device density is improved, but parasitic capacitance increases
Solution Approach 1:
The patent implements nested stacking where multiple capacitor structures are vertically nested within each other. Each capacitor unit consists of stacked plates and dielectric layers, with subsequent capacitors nested in the vertical space above or below previous units. This nesting approach achieves high device density by utilizing the third dimension, while the regular alternating pattern of top and bottom plates helps control parasitic capacitance through symmetric charge distribution.
3Area of stationary object
If capacitor array extension in X direction is reduced, then area is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent resolves the area versus precision contradiction by moving the expansion direction from the X-plane to the vertical Z-dimension. Instead of extending capacitor arrays horizontally which requires precise lateral alignment, the design stacks capacitor plates vertically where the critical alignment is in the Z-direction. This dimensional transition reduces the X-direction footprint while the vertical stacking process can accommodate standard fabrication tolerances for plate thickness and spacing, thereby reducing manufacturing precision requirements in the planar direction.
Data Source
AI summary
The disclosure provides a capacitor array. The capacitor array includes one or more first metal plates vertically stacked parallel to each other. A second metal plate is horizontally stacked to couple one end of each first metal plate of the one or more first metal plates. One or more third metal plates are vertically stacked parallel to the one or more first metal plates. Each third metal plate of the one or more third metal plates is stacked between two first metal plates.