Low Permittivity Layers Reduce Parasitic Capacitance in Memory Devices
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Solution Overview
Problem
Variable resistance memory devices face reduced read/write operation speeds due to high parasitic capacitance between bit lines and word lines, which existing techniques have not adequately addressed.
Innovation Solution
The implementation of low permittivity layers and air gaps between bit lines and word lines, with specific configurations of dielectric layers to minimize parasitic capacitance, including a first low permittivity layer filling spaces between bit lines and partially filling spaces between memory cells on word line surfaces, and a second low permittivity layer filling spaces between word lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dielectric layers are used to fill spaces between bit lines and word lines, then the structural integrity and insulation are improved, but parasitic capacitance increases reducing read/write speed
Solution Approach 1:
The patent changes the permittivity parameter of the dielectric material by introducing air gaps (permittivity ≈ 1) into the dielectric layer, creating a composite structure with lower effective permittivity. This reduces parasitic capacitance between bit lines and word lines while maintaining insulation, thereby improving read/write operation speed without sacrificing reliability
Solution Approach 2:
The patent creates a composite dielectric structure combining traditional dielectric materials with air gaps. This composite approach allows the structure to maintain the insulation properties of the dielectric material while the air gaps reduce the overall permittivity, thus reducing parasitic capacitance and improving signal transmission speed
2Ease of manufacture
If traditional dielectric materials are used to fill spaces between signal wirings, then ease of manufacture is improved, but parasitic capacitance increases reducing operation speed
Solution Approach 1:
The patent modifies the permittivity parameter of the fill material by introducing air gaps through existing fabrication processes. The air gaps are formed by controlling the deposition process to create voids, which reduces effective permittivity without requiring entirely new manufacturing techniques, thus maintaining ease of manufacture while improving operation speed
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces parasitic capacitance, enhancing the read/write operation speed of memory devices by utilizing low permittivity materials and air gaps to minimize electrical interference.
Implementation Method 1
A large parasitic capacitance may be generated between the bit lines and between the word lines due, in part, to dielectric layers configured to fill spaces between the bit lines and between the word lines. The parasitic capacitance between signal wirings of the memory device reduces a read/write operation speed of the memory device.
Implementation Method 2
The first and second low permittivity layers have lower permittivity than the first and second dielectric layers.
Data Source
AI summary
A memory device is provided. The memory device includes bit lines that extend in a first direction on a substrate, word lines configured to vertically cross the bit lines, memory cells formed at intersections of the bit lines and the word lines, a first low permittivity layer configured to fill spaces between the bit lines and partially fill spaces between the memory cells formed on bottom surfaces of the word lines, a first dielectric layer stacked on an upper surface of the first low permittivity layer between the memory cells, a second dielectric layer configured to fill spaces between the memory cells formed on upper surfaces of the bit lines, and a second low permittivity layer stacked on an upper surface of the second dielectric layer and configured to fill spaces between the word lines. The first and second low permittivity layers have lower permittivity than the first and second dielectric layers.