Low-Permittivity Spacers for DRAM Digit-Line Capacitive Coupling
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Solution Overview
Problem
Highly integrated DRAM architectures face capacitive coupling issues between tightly-packed conductive structures, which hinder scaling and performance.
Innovation Solution
Incorporating low-permittivity spacers between digit-lines and conductive interconnects to reduce capacitive coupling, using materials with dielectric constants below 5, such as porous silicon dioxide or carbon-doped silicon dioxide, to alleviate coupling and enable higher integration levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conductive structures are tightly packed to increase integration density, then productivity and quantity increase, but capacitive coupling between structures increases causing harmful interference
Solution Approach 1:
Low-permittivity spacers are introduced as intermediary structures between digit-lines and conductive interconnects. These spacers act as mediators that reduce capacitive coupling while allowing the conductive structures to remain tightly packed for high integration density. The spacers are formed with materials having dielectric constants below 5, such as porous silicon dioxide or carbon-doped silicon dioxide, positioned at critical interfaces where capacitive coupling occurs.
Solution Approach 2:
The permittivity parameter of the dielectric material between conductive structures is changed from conventional values to low values below 5. This parameter change reduces the capacitive coupling coefficient between digit-lines and interconnects, allowing tight packing without the harmful capacitive effects that would normally limit integration density.
2Object-generated harmful factors
If low-permittivity spacers are added to reduce capacitive coupling, then harmful factors decrease, but device complexity and manufacturing steps increase
Solution Approach 1:
The formation of low-permittivity spacers is merged with existing spacer formation processes in the fabrication sequence. The spacers are formed using deposition and etch-back steps that are integrated into the digit-line and interconnect formation process, rather than being added as completely separate process modules. This reduces the overall complexity increase despite the additional functional requirement.
3Object-generated harmful factors
If low-permittivity spacers are added to reduce capacitive coupling, then harmful factors decrease, but manufacturing precision requirements increase
Solution Approach 1:
The low-permittivity spacers are formed using self-aligned processes where the spacer material is deposited conformally on the digit-lines and then etched back. The digit-line structures themselves serve as the alignment reference for spacer formation, eliminating the need for separate alignment steps and reducing manufacturing precision requirements despite the critical function of the spacers.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The use of low-permittivity spacers effectively mitigates capacitive coupling, allowing for the scaling of DRAM architectures to higher integration levels and improving performance by reducing interference between interconnects and digit-lines.
Implementation Method 1
capacitive coupling occurs between tightly-packed conductive structures
Implementation Method 2
low-permittivity spacers (e.g., spacers having dielectric constants below 5, below 3.9, etc.) are provided between digit-lines and conductive interconnects adjacent the digit-lines
Data Source
AI summary
Some embodiments include an integrated assembly having active-region-pillars extending upwardly from a base. Each of the active-region-pillars has a pair of storage-element-contact-regions, and a digit-line-contact-region between the storage-element-contact-regions. The integrated assembly includes, along a cross-section, a first digit-line-contact-region adjacent a first storage-element-contact-region. The first digit-line-contact-region is recessed relative to the first storage-element-contact-region. A first digit-line is coupled with the first digit-line-contact-region. A second digit-line is laterally offset from the first digit-line. An insulative material is between the first digit-line and the first storage-element-contact-region. A cup-shaped indentation extends into the insulative material and the first storage-element-contact-region. Insulative spacers are along sidewalls of the first and second digit-lines, and include first material. First and second insulative pillars are over the first and second digit-lines, and include second material. Some embodiments include methods of forming integrated assemblies.