Low Pin Count Bus Error Detection via Sideband Signals
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Solution Overview
Problem
Computer bus systems lacking error correction capabilities can lead to silent data corruption, which may result in catastrophic failures, especially in systems with reduced pin count buses that do not include error reporting or correction signals.
Innovation Solution
The implementation of a bus interface circuit that couples to a serial bus and drives error values on sideband signal lines to detect and report parity errors, allowing for error detection and correction even in low pin count buses with limited signal lines, by using supplementary sideband signals to convey error information.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If error detection and reporting capabilities are added to a low pin count bus, then system reliability is improved, but device complexity increases due to additional sideband signal lines
Solution Approach 1:
The patent introduces sideband signal lines as an additional dimension for error communication. Instead of modifying the existing bus protocol or using additional pins on the bus itself, the invention adds separate sideband lines that operate independently, allowing error information to be conveyed through a different dimensional space (sideband vs. main bus signals).
Solution Approach 2:
The sideband signal lines act as intermediaries between the low pin count bus and the error detection mechanism. These intermediary lines carry error information without interfering with the primary data transmission function of the bus, allowing error reporting to be added without directly modifying the core bus protocol.
2Reliability
If parity information is transmitted during the addressing portion of a read request, then error detection is enabled without additional signal lines, but the addressing portion of the bus protocol must be modified to accommodate parity bits
Solution Approach 1:
The patent makes the address lines serve multiple functions: they carry both the address information and the parity information for error detection. By multiplexing these functions onto the same physical lines, the system achieves error detection capability without adding separate dedicated parity transmission lines, thus reducing overall device complexity.
Solution Approach 2:
The invention uses only the necessary portion of the address signal duration to transmit parity information. Rather than requiring a complete separate parity transmission phase, the system incorporates parity bits into the existing address transmission window, utilizing partial action within the addressing portion to achieve error detection with minimal protocol modification.
Data Source
AI summary
Systems and methods that implement communication of error information on a bus, including a bus having a small number of pins are disclosed. In one embodiment, an apparatus includes an interface circuit configured to couple to a bus and one or more sideband signals. The sideband signals may be used to communicate error information such as parity information for a bus that does not otherwise have this capability. In some embodiments, parity information may be driven on the bus during a portion of a bus transaction corresponding to unused address bits.