Low-Pin NVM Interface for 3D IC Pin Reduction
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Solution Overview
Problem
Current non-volatile memory (NVM) interfaces, particularly for one-time-programmable (OTP) memory in 3D ICs, face challenges due to high pin counts, which limit their integration and scalability, and are inefficient in accommodating read and program speed discrepancies, leading to increased complexity and costs.
Innovation Solution
A low-pin-count NVM interface that utilizes only two signals, PGM and CLK, for program control and clock, allowing for reduced pin count by sharing pins and multiplexing, enabling efficient integration into integrated circuits and 3D ICs, with the ability to chain or broadcast signals to reduce external pin requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional NVM interfaces are used, then programming and reading capabilities are maintained, but pin count increases and integration efficiency decreases
Solution Approach 1:
The patent implements multi-functionality by enabling the PGM pin to serve multiple purposes: it acts as both the program control signal input and the data output pin (PGM/Q). This allows the interface to maintain full programming and reading capabilities while reducing the total pin count, directly resolving the contradiction between device complexity and reliability
Solution Approach 2:
The patent merges the data output function into the existing PGM pin by implementing a tri-state buffer that can drive the PGM/Q pin in read mode. This consolidation combines multiple functions (program control and data output) into a single pin, reducing pin count while preserving all necessary capabilities
2Area of stationary object
If more pins are used for NVM interface, then programming and reading operations are supported, but footprint and cost increase
Solution Approach 1:
The PGM pin is designed as a universal pin that handles both program control and data output functions. This multi-functionality eliminates the need for separate dedicated pins for each operation, thereby reducing the overall footprint while maintaining full adaptability for programming and reading operations
Solution Approach 2:
The patent resolves the pin count issue by utilizing time-multiplexing and state transitions rather than adding spatial pins. The PGM/Q pin transitions between different functional states (program mode, read mode, output mode) over time, effectively adding functionality without increasing physical pin count or footprint
3Ease of manufacture
If conventional interfaces are used, then NVM functionality is achieved, but manufacturing complexity and defects increase
Solution Approach 1:
The patent simplifies the interface structure by merging multiple control signals and data lines into a reduced set of pins (PGM, CLK, CS). This consolidation reduces the complexity of the interface structure, making it easier to manufacture and integrate into 3D ICs while maintaining full NVM functionality
Data Source
AI summary
A low-pin-count non-volatile (NVM) memory to be provided in an integrated circuit for a 3D IC to repair defects, trim devices, or adjust parameters is presented here. At least one die in a 3D IC can be built with at least one low-pin-count OTP memory. The low-pin-count OTP memory can be built with a serial interface such as I2C-like or SPI-like of interface. The pins of the low-pin-count OTP in at least one die can be coupled together to have only one set of low-pin-count bus for external access. With proper device ID, each die in a 3D IC can be accessed individually for soft programming, programming, erasing, or reading. This technique can improve the manufacture yield, device, circuit, or logic performance or to store configuration parameters for customization after 3D IC are built.