Low-Pin IC Testing via Segmented Scan Clocks
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Solution Overview
Problem
Integrated circuits with limited pins face challenges in achieving high-quality testing due to reduced pin counts, which impact test results and exceed power budgets during scan shifting, necessitating a low-pin scanning architecture that enables full test suites while managing scan power.
Innovation Solution
A method and apparatus for low-pin count testing involving the generation of scan test circuitry with deserializers, decompressors, scan chain registers, and a controller that interleaves scan clocks to shift registers independently, enabling efficient test pattern compression and decompression, and on-product clock generation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If test data compression is applied to reduce pin count, then the number of test pins is reduced, but test quality and completeness deteriorate
Solution Approach 1:
The patent divides the scan chain into multiple segments or groups, each controlled by separate scan clocks. This segmentation allows independent control of different portions of the scan chain, enabling complete test coverage while using fewer pins through compressed test data application.
Solution Approach 2:
The patent employs periodic scanning where scan clocks are applied in alternating phases to different groups of scan chains. This periodic action allows complete test coverage over multiple cycles while reducing instantaneous pin requirements, as not all scan chains need to be active simultaneously.
2Speed
If scan shifting is performed on all scan chains simultaneously, then testing speed is improved, but power consumption exceeds the power budget
Solution Approach 1:
The patent segments the scan chains into multiple groups, each controlled by a separate scan clock signal. This allows different groups to be scanned at different times, reducing instantaneous switching activity and power consumption while maintaining overall testing speed through parallel group operation.
Solution Approach 2:
The patent implements periodic scanning where scan clocks are alternately applied to different groups of scan chains in phases. This periodic action distributes the switching activity over time, preventing power budget exceedance while maintaining high testing throughput through systematic rotation of active scan groups.
3Device complexity
If low-pin test architecture is implemented, then device complexity is reduced, but the ability to perform complete test suites deteriorates
Solution Approach 1:
The patent divides the test architecture into segmented scan chain groups with dedicated control logic for each group. This segmentation enables complete test suite execution through systematic rotation and combination of group tests, while keeping individual group complexity low and manageable with fewer pins.
Solution Approach 2:
The patent uses periodic scanning sequences that systematically activate different groups of scan chains over multiple cycles. This periodic action ensures complete test coverage of all scan chains and logic elements while using a simple, low-pin architecture that cycles through different scan configurations.
Data Source
AI summary
A method and apparatus to apply compressed test patterns using a very pin-limited test apparatus to a chip design for use in semiconductor manufacturing test is disclosed. Compression circuitry is inserted into the circuit design and the compressed signals manipulated for communication over a serial interface. On a test apparatus, ATPG may be run, assuming a parallel test interface, resulting in test patterns that may be compressed into a parallel format and then converted into a serial signal. On chip, the serial signal is parallelized, decompressed, and then shifted into the scan chains. An inserted controller generates clocks and various control signals. Conventional test patterns from ATPG may be generated and applied during testing without the need to modify the ATPG program saving time and resources. Hierarchical testing of integrated circuits built with a multiplicity of cores, each having its own embedded compression logic, is also supported.