Low-Power Assertion Checker Control for Selective Simulation Coverage
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Solution Overview
Problem
Current low-power design verification methods lack the flexibility to selectively enable or disable low-power assertion (LPA) checkers during simulation, leading to inefficiencies and potential errors due to the need for full ON or full OFF configurations, which does not allow for fine-grained control over individual assertions.
Innovation Solution
Implement methods and systems to couple LPA checkers with low-power objects, enabling selective enabling or disabling based on predefined criteria such as memory space, processing time, or processing power, using System Verilog Assertions (SVA) language, allowing for finer control over LPA checkers through assertion control techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If LPA checkers are fully enabled during simulation, then verification coverage is improved, but simulation time and computational resources increase
Solution Approach 1:
The patent segments the LPA checker functionality into individually controllable assertion units. Each assertion can be independently enabled or disabled based on verification needs, allowing selective execution of specific checks rather than running all assertions uniformly. This segmentation enables fine-grained control over simulation resources while maintaining necessary verification coverage.
Solution Approach 2:
The patent implements dynamic control of LPA checker assertions through runtime enable/disable mechanisms. Assertions can be activated or deactivated based on simulation progress, design conditions, or verification priorities. This dynamic approach allows the verification process to adapt resource consumption to actual needs at different simulation stages.
2Productivity
If LPA checkers are fully disabled to reduce simulation overhead, then simulation efficiency is improved, but verification completeness deteriorates
Solution Approach 1:
By dividing the LPA checker into discrete, independently controllable assertions, the patent enables selective activation of only those checks necessary for current verification objectives. This segmentation allows the system to maintain verification completeness for critical functions while disabling non-essential checks to preserve simulation efficiency.
Solution Approach 2:
The patent utilizes parameter-based control mechanisms to adjust assertion behavior based on simulation context. Control parameters such as enable/disable flags, priority levels, and condition-based activation allow the verification system to optimize between completeness and efficiency by changing assertion parameters dynamically rather than using fixed on/off states.
3Ease of operation
If fine-grained control of individual assertions is implemented, then control precision is improved, but system complexity increases
Solution Approach 1:
The patent implements a universal control framework that manages individual assertions through standardized mechanisms. The same control interface and methodology can be applied to any assertion within the LPA checker, providing fine-grained control without requiring unique handling for each assertion. This multi-functional approach simplifies the control mechanism while maintaining precision.
Solution Approach 2:
The patent employs parameter-based control where assertions are managed through configurable parameters rather than complex structural modifications. By using enable/disable parameters, priority levels, and condition flags, the system achieves fine-grained control through simple parameter adjustments rather than intricate control logic, thereby reducing overall system complexity.
Data Source
AI summary
A computer-implemented method for validation of a low-power design for an electronic circuit. The method includes accessing, by a processing device, the low-power design of the electronic circuit including one or more low-power elements. The method further includes selecting, from the design of the electronic circuit, a domain and a power activity, and enabling an assertion component configured to control the one or more low-power elements in the domain, the low-power elements performing the power activity.