Low-Power Cache With Data Bus Inversion for SoC Transfers
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Solution Overview
Problem
Computer systems with system-on-chip (SOC) architectures experience high power consumption due to frequent data transfers over wide internal buses, leading to signal switching that causes power and ground bounce, glitches, and noise, particularly in portable devices powered by batteries.
Innovation Solution
Implementing a cache system that selectively stores data in inverted formats based on transition analysis to reduce the number of signal transitions during data transfers, using metadata bits to determine the inversion state of data words.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If data is transferred frequently over wide internal buses in SOC, then data access speed is improved, but power consumption increases due to repeated switching of highly-capacitive bus lines
Solution Approach 1:
The patent applies data bus inversion (DBI) technique where data bits are inverted (0 becomes 1, 1 becomes 0) before transmission on the bus. By analyzing the data pattern and inverting when it would cause excessive transitions, the patent reduces the number of switching events on highly-capacitive bus lines, thereby reducing power consumption while maintaining data access speed. The inversion is detected and corrected at the receiving end to restore original data values.
2Productivity
If multiple signal lines switch logic states simultaneously during data transfers, then data transfer efficiency is improved, but power and ground bounce occurs causing glitches and noise
Solution Approach 1:
The patent uses data bus inversion to modify the data pattern being transmitted. By inverting data bits strategically, the patent reduces simultaneous switching of multiple signal lines, thereby minimizing power and ground bounce effects that cause glitches and noise. This allows efficient data transfer while reducing harmful electromagnetic interference and signal integrity issues.
Solution Approach 2:
The patent introduces an intermediary inversion detection and correction mechanism at the receiving end. This intermediary component detects inverted data patterns and corrects them back to original values, allowing the transmitting end to use inversion for reducing simultaneous switching without affecting the receiving end's ability to interpret data correctly. This mediator enables efficient transfer while eliminating harmful bounce effects.
Data Source
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AI summary
A cache includes an upstream port, a cache memory for storing cache lines each having a line width, and a cache controller. The cache controller is coupled to the upstream port and the cache memory. The upstream port transfers data words having a transfer width less than the line width. In response to a cache line fill, the cache controller selectively determines data bus inversion information for a sequence of data words having the transfer width, and stores the data bus inversion information along with selected inverted data words for the cache line fill in the cache memory.