Low Power Circuit Test Generation via Selective Domain Activation
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Solution Overview
Problem
Existing methods for testing low-power integrated circuits face challenges such as excessive power consumption and heat dissipation during testing, which can lead to inaccurate results and potential damage to the ICs, as they typically require all power domains to be powered up, unlike actual operational modes where only a fraction of the chip is active.
Innovation Solution
A method is introduced to map power modes of the circuit to test modes, allowing for systematic testing by powering down non-essential domains during physical testing, using the Common Power Format to identify and isolate powered and unpowered logic, and generating test vectors that target only active logic, thereby minimizing power consumption and avoiding false results.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If all power domains are powered up during testing, then complete coverage of the circuit can be achieved, but power consumption and heat dissipation increase excessively
Solution Approach 1:
The patent segments the power domains into multiple groups, allowing selective powering up of only those domains that need to be tested in a given test mode. This is achieved by partitioning the circuit into power domains and enabling independent power control for each domain, thereby reducing overall power consumption while maintaining testing coverage for active domains.
Solution Approach 2:
Instead of powering up all power domains completely, the patent applies partial action by powering up only the subset of domains required for specific test scenarios. This partial powering approach reduces energy consumption while still achieving the necessary testing objectives for the active portions of the circuit.
2Reliability
If all power domains are powered up during testing, then all circuit elements can be tested, but heat dissipation may damage the IC
Solution Approach 1:
The patent segments power domains and enables selective activation based on test requirements. By dividing the circuit into manageable power domains that can be independently controlled, the system can limit heat generation to only those domains being tested, preventing thermal damage to the entire IC while maintaining fault detection capability.
3Loss of energy
If power management techniques are applied at physical implementation phase, then power optimization is achieved, but the original RTL design intent cannot be verified
Solution Approach 1:
The patent applies preliminary action by incorporating power domain information and power mode definitions into the RTL design phase itself. This allows power management considerations to be addressed during early design stages, enabling verification of design intent against power optimization requirements before physical implementation, thus preventing loss of design intent information.
Data Source
AI summary
In the field of integrated circuit design and testing, especially directed towards integrated circuits intended to operate at low power, a method and system are provided for circuit design and simulation and testing for mapping portions of a circuit, such as a power domain or portion of a power domain, to a test mode. Thereby only those portions of the circuit which need to be powered up in a particular test mode are powered up both in the design (simulation) phase and in the actual testing. This conserves power usage during actual testing as against powering up all portions of the circuit, which is not desirable during the testing of the circuit after manufacture. This ensures that the power conditions required to excite and observe any circuit faults during testing exist for the power conditions that are applied during, for instance, manufacturing testing. By automatically partitioning the faults to remove those that cannot be excited or observed during manufacturing and testing, the testability of the device in terms of its partitions or parts will accurately reflect the power state of the logic portions of the circuit.