Low-Power Clock MUX Control to Mitigate BTI Ageing
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Solution Overview
Problem
Integrated circuits face reliability issues due to Bias Temperature Instability (BTI) ageing, particularly in MOS transistors, which lead to increased threshold voltage and static operation errors, resulting in deteriorated clock duty cycles and circuit failures.
Innovation Solution
A low frequency signal is introduced during low power mode to balance BTI ageing in digital logic circuits, with a counter ensuring equal stress and recovery cycles for PMOS and NMOS transistors in a clock distribution circuit, using a multiplexer and very low frequency clock to toggle states and maintain balanced duty cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If a digital logic circuit operates in low power mode with static logic values, then power consumption is reduced, but BTI ageing effects increase causing threshold voltage shifts and circuit failures
Solution Approach 1:
The patent applies periodic action by introducing a low-frequency clock signal that periodically toggles the logic values in the circuit during low power mode. This periodic switching causes transistors to alternately experience stress and recovery phases, preventing cumulative BTI degradation while maintaining low average power consumption. The clock signal frequency is specifically chosen to be low enough to maintain power savings but high enough to provide sufficient stress-recovery cycles.
Solution Approach 2:
The patent changes the operational parameters of the circuit during low power mode by switching from static logic values to dynamic low-frequency clocked operation. This parameter change involves modifying the clock signal frequency and the logic state transitions to optimize the balance between power consumption and BTI mitigation. The circuit transitions between different operational states (high power mode with high-frequency clock, low power mode with low-frequency clock) by changing frequency and activity parameters.
2Loss of energy
If DC voltage is applied to MOS transistor gates without drain current, then transistor stress is reduced, but BTI effects accumulate causing threshold voltage increase
Solution Approach 1:
The patent implements periodic action by using a low-frequency clock signal to continuously switch the logic states of circuit elements during low power mode. This periodic switching ensures that transistors alternate between stress conditions (when biased without drain current) and recovery conditions (when drain current flows), preventing permanent BTI degradation. The timing and duration of these cycles are controlled to optimize both energy efficiency and transistor reliability.
3Ease of operation
If logic values remain fixed during low power mode, then circuit operation is simplified, but clock duty cycle deteriorates due to unbalanced BTI stress
Solution Approach 1:
The patent applies periodic action by introducing a low-frequency clock signal that systematically toggles logic values through defined sequences. This periodic operation maintains relatively simple circuit architecture while ensuring that PMOS and NMOS transistors experience balanced stress and recovery cycles. The clock signal propagates through the circuit in a controlled manner, preventing duty cycle deterioration that would result from unbalanced static operation.
Solution Approach 2:
The patent introduces dynamics into the circuit operation during low power mode by transitioning from static fixed logic values to dynamic low-frequency clocked operation. This dynamic behavior involves controlled signal propagation through logic elements, where the clock signal rhythmically changes state and triggers corresponding changes in logic values. This dynamic operation balances BTI stress distribution while maintaining operational simplicity through systematic clocking.
Data Source
AI summary
An integrated circuit includes a digital logic circuit, a multiplexer (MUX) having a first and a second data input, a control input, and an output coupled to an input of the digital logic circuit. The second data input is coupled to receive a high frequency clock signal. The integrated circuit includes a very low frequency (VLF) clock is configured to provide a VLF clock signal when enabled, and a counter coupled to receive the VLF clock signal and configured to toggle an output of the counter upon counting a predetermined number of cycles of the VLF clock signal. The output of the counter is coupled to the first data input of the MUX. The MUX is configured to provide the first data input as the output of the MUX during a low power mode, and otherwise to provide the second data input as the output of the MUX.