Low Power Computational Imaging Hardware Architecture
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Solution Overview
Problem
Computational imaging technologies face challenges in adopting low power consumption and flexible hardware architectures, particularly in portable devices, due to high computational resource requirements and sensitivity to latency, making it difficult to implement efficiently in customized hardware.
Innovation Solution
A computing device with multiple vector processors, hardware accelerators, and a memory fabric, along with a power management module, is designed to provide low power computational imaging capabilities by dynamically managing power supply and processing tasks, enabling efficient image and video processing in portable devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If computational imaging processes images and videos at high resolution and frame rates, then image quality and processing capability are improved, but power consumption increases significantly
Solution Approach 1:
The system segments the computational imaging workload into distinct processing stages handled by specialized hardware components: a host processor for control and coordination, vector processors for parallel mathematical operations on image data, and hardware accelerators for specific computational tasks. This segmentation allows each component to operate efficiently at optimized power levels while collectively delivering high-resolution, high-frame-rate processing capability.
Solution Approach 2:
The system dynamically manages power consumption by enabling or disabling specific processing components based on operational requirements. The host processor can dynamically allocate tasks to vector processors or hardware accelerators only when needed, allowing the system to scale power consumption according to the actual computational demand rather than operating at maximum capacity continuously.
2Adaptability or versatility
If computational imaging uses regular computer processors, then implementation flexibility is maintained, but processing speed and computational performance are insufficient
Solution Approach 1:
The vector processors are designed with a universal architecture that can execute various computational imaging algorithms through programmable instruction sets. Rather than hardcoding specific functions, the vector processors can be configured to perform different operations (e.g., image filtering, feature detection, depth map generation) by loading appropriate instruction sequences, thereby maintaining implementation flexibility while delivering high computational performance through specialized hardware acceleration.
Solution Approach 2:
The host processor serves as an intermediary between the flexible software layer and the high-performance hardware components. It manages the division of labor by offloading computationally intensive tasks to vector processors and hardware accelerators while retaining control over algorithm selection and parameter configuration, thus bridging the gap between software flexibility and hardware performance.
3Loss of time
If computational imaging is designed for quick processing to meet latency requirements, then user experience is improved, but power consumption and computational resource requirements increase
Solution Approach 1:
The system performs preliminary processing actions by pre-computing and caching frequently used data structures and intermediate results in high-speed memory. For example, lookup tables for common image processing operations and pre-processed depth information from previous frames are maintained in fast memory, allowing the vector processors and hardware accelerators to retrieve this data without incurring full processing latency while consuming minimal additional power.
Solution Approach 2:
The system maintains continuous processing pipelines where data flows continuously through the vector processors and hardware accelerators without interruption. By keeping the processing pipeline full and avoiding idle cycles, the system achieves low latency through sustained high-speed operation rather than periodic bursts, thereby reducing the average power consumption compared to stop-start processing modes while maintaining low latency performance.
Data Source
AI summary
The present application discloses a computing device that can provide a low-power, highly capable computing platform for computational imaging. The computing device can include one or more processing units, for example one or more vector processors and one or more hardware accelerators, an intelligent memory fabric, a peripheral device, and a power management module. The computing device can communicate with external devices, such as one or more image sensors, an accelerometer, a gyroscope, or any other suitable sensor devices.