Low Power Context Storage for Processor Context Retention
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Solution Overview
Problem
Processor devices on high-availability platforms face challenges in maintaining low latency for power state transitions due to leakage in volatile local CPU storage, which increases battery life reduction and requires software-based state restoration, increasing exit latency.
Innovation Solution
A system that utilizes a separate nominal power domain with low power context storage to retain processor context information, allowing for efficient storage and retrieval during power state transitions, reducing the need for software-based state restoration and minimizing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If CPU context information is retained in volatile local CPU cache, then fast access is achieved, but power leakage increases making it infeasible for low power modes
Solution Approach 1:
The patent divides the context storage system into two separate components: volatile local CPU cache for fast access during active operation, and non-volatile external storage for persistent storage during low power modes. This segmentation allows each component to optimize for its specific function without compromising the other.
Solution Approach 2:
The patent introduces a context storage management mechanism that acts as an intermediary between the volatile local cache and non-volatile external storage. This intermediary manages the transfer and synchronization of context information, enabling seamless operation across different power states.
2Use of energy by stationary object
If CPU context information is not retained in hardware, then power consumption is reduced, but exit latency from low power states increases due to software-based restoration
Solution Approach 1:
The patent performs preliminary actions by saving CPU context information to non-volatile external storage before entering low power modes. This advance preparation ensures that context data is already available when exiting the low power state, eliminating the need for time-consuming software-based restoration and enabling fast resume operation.
3Speed
If processor core state restoration operates at high power level, then fast restoration is achieved, but battery life decreases significantly
Solution Approach 1:
The patent changes the operational parameters of context storage by transitioning from volatile to non-volatile storage media. This parameter change allows the system to maintain fast restoration speeds while operating at significantly lower power levels during low power modes, as non-volatile storage requires minimal power to retain data without active refresh operations.
Data Source
AI summary
A method and system for saving and/or retrieving context information of a processor core for a power state transition. The processor core resides in a complex power domain variously transitioning between a plurality of power states. The processor core includes a local context storage area for storage and retrieval of processor core context information. A low power context storage resides in a nominal power domain external to the complex power domain. Context information of the processor core is stored to the low power context storage based on whether a power state transition of the complex power domain includes a transition to power down the processor core.