Low-Power Counting Circuit Using Divider-Multiplier Stages
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional counting circuits in memory systems require high power and large circuit footprints, making them impractical for mobile devices with increasing operating frequencies and smaller form factors.
Innovation Solution
A low power counting circuit design that includes a frequency divider to reduce the clock signal frequency, a counter to track signal transitions, and a frequency multiplier to restore the original frequency, utilizing a reduced number of D latches and signal transitions, thereby minimizing power consumption and circuit size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conventional counting circuits are used to track signal transitions, then counting functionality is achieved, but power consumption is high and circuit footprint is large
Solution Approach 1:
The counting circuit is segmented into multiple stages, with each stage counting a specific number of transitions (e.g., 2, 4, 8) before incrementing the final count. This segmentation allows the use of fewer high-power D latches while maintaining accurate transition counting functionality across the entire clock signal period.
Solution Approach 2:
The counting circuit utilizes periodic sampling of the clock signal transitions through multiple counting stages that operate at different frequencies. By periodically incrementing counts at different stages based on the clock signal period, the circuit achieves accurate transition counting with reduced power consumption compared to continuous counting at full clock frequency.
2Area of stationary object
If conventional counting circuits are used to track signal transitions, then counting functionality is achieved, but circuit size is large
Solution Approach 1:
The counting circuit is divided into multiple counting stages, each handling a portion of the total transition count. This segmentation reduces the number of D latches required in each stage, thereby reducing the overall circuit footprint while maintaining the ability to accurately track the total number of clock signal transitions.
Solution Approach 2:
The counting function is extended to multiple dimensions by implementing hierarchical counting stages. Instead of using a single large counter, the circuit uses multiple smaller counters operating at different levels, where each stage contributes to the final count. This dimensional approach reduces the circuit footprint by distributing the counting function across multiple smaller units.
3Speed
If operating frequency is increased in mobile devices, then performance is improved, but power consumption and circuit size requirements increase
Solution Approach 1:
The counting circuit operates periodically at the clock signal frequency, with each counting stage synchronized to specific phases of the clock cycle. This periodic operation allows the circuit to maintain accurate transition counting at high operating frequencies while minimizing power consumption by keeping D latches in low-power states during non-counting periods.
Solution Approach 2:
The circuit dynamically adjusts its operating parameters based on the clock signal frequency. By changing the counting stage activation thresholds and timing based on the input clock frequency, the circuit maintains optimal power consumption and counting accuracy across a range of operating frequencies, enabling mobile devices to achieve high performance without proportionally increased power consumption.
Data Source
AI summary
Apparatuses and methods for low power counting circuits are described herein. An example apparatus may include a frequency divider configured to receive an input clock signal and adjust a frequency of the clock signal to provide an intermediate clock signal. The apparatus may further include a counter coupled to the frequency divider and configured to receive the intermediate clock signal. The counter may further be configured to provide a plurality of timing signals based on the intermediate clock signal. The apparatus may further include a frequency multiplier including a plurality of logic gates. Each of the plurality of logic gates may be coupled to the counter and configured to receive a respective first timing signal of the plurality of timing signals and at least one of the intermediate clock signal or a respective second timing signal of the plurality of timing signals.