Low Power Current Comparator for Switched Mode Regulators

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Solution Overview

Problem

Switched mode regulators face challenges in achieving high power efficiency and design simplicity due to the limitations of traditional voltage comparators, which consume excessive power and current, especially when operating at low current levels.

Innovation Solution

A low power current comparator is developed, incorporating a level-shifted NMOS inverting amplifier with feedback clamp transistors, which reduces power and current requirements by using NMOS and PMOS transistors to form a current limited inverter or differential amplifier stage, limiting supply current through IBIAS1 and IBIAS2.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If traditional voltage comparators are used in switched mode regulators, then comparison function is provided, but power consumption and current draw are excessive

Engineering Contradiction:
Improvepower consumptionVSAvoidcomparison accuracy
Core Design Contradiction:
Use of energy by moving objectVSReliability

Solution Approach 1:

The patent changes the operating parameters of the comparator by using current-mode operation instead of voltage-mode, and by implementing dynamic biasing that adjusts operating currents based on signal conditions. This allows accurate comparison while reducing average power consumption significantly

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The comparator employs periodic switching of the series element between fully conducting and fully off states, enabling efficient charge transfer to the load while minimizing power dissipation during switching transitions

Inventive Principle:
Principle #19Periodic action

2Loss of energy

If switched element operates in fully conducting or fully off state, then power dissipation is minimized, but output voltage control becomes challenging

Engineering Contradiction:
Improvepower dissipationVSAvoidoutput voltage control
Core Design Contradiction:
Loss of energyVSEase of operation

Solution Approach 1:

The patent implements feedback control where the comparator continuously monitors the output voltage and adjusts the duty cycle of the switching element accordingly. This maintains output voltage regulation while keeping the switch in extreme states for minimal power loss

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The switching element serves multiple functions: it acts as a variable resistor during on-state for charge transfer, as an open circuit during off-state for energy storage, and as a controlled switch for regulating output voltage, all while maintaining low power dissipation

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Use of energy by moving object

If current comparator uses feedback clamp transistors with level-shifted amplifier, then power and current requirements are reduced, but circuit complexity increases

Engineering Contradiction:
Improvecurrent requirementsVSAvoidcircuit structure
Core Design Contradiction:
Use of energy by moving objectVSDevice complexity

Solution Approach 1:

The patent combines multiple functions into integrated circuit blocks: the feedback clamp transistors are merged with the level-shifted amplifier stage, and the current mirror circuits are integrated with the comparator logic. This reduces component count and parasitic effects while achieving low power operation

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The level-shifted amplifier acts as an intermediary stage that translates small current differences from the comparator into sufficient voltage swings for the output stage, enabling accurate comparison with minimal input current while driving the power switch effectively

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS9024603B2Low power current comparator for switched mode regulator
Publication Date: 2015.05.05 SYNAPTICS INC
  • US9024603B2 patent drawing
  • US9024603B2 patent drawing
  • US9024603B2 patent drawing

AI summary

A current comparator comprising a first NMOS transistor having a drain coupled to VDD, a source and a gate. A first PMOS transistor having a source coupled to the source of the first NMOS transistor to form an input, a drain coupled to VSS and a gate coupled to the gate of the first NMOS transistor. A second NMOS transistor having a drain coupled to VDD, a source and a gate coupled to the input. A first bias current source having an input coupled to the source of the second NMOS transistor and an output. A second bias current source having an input coupled to the drain of the first NMOS transistor and an output coupled to the gate of the first NMOS transistor. A third NMOS transistor having a drain coupled to the gate of the first NMOS transistor to form an output, a source and a gate.