Low-Power DEB-TED Decoder With Selective SEC-DEC Activation
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Solution Overview
Problem
Conventional error correction schemes for multiple-bit errors in memory devices require significant circuitry, consume excessive power, and result in longer latency, making them unsuitable for low-power integrated circuits.
Innovation Solution
A double error correction (DEC) system with reduced power consumption is implemented using a syndrome generator, controller, error location decoders, and a multiplexer, which selectively activates single or double error correction mechanisms based on error detection signals to minimize active components and power usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If DEC-TED circuitry is utilized to correct single errors, then error correction capability is improved, but power consumption increases
Solution Approach 1:
The error correction system is divided into separate SEC and DEC modules that operate independently. The controller selectively activates only the necessary module based on error detection, avoiding the power consumption of running a full DEC-TED system for all error cases.
Solution Approach 2:
The system dynamically switches between SEC and DEC correction modes based on the detected error type. This dynamic adaptation allows the system to use minimal power for single-bit errors while providing enhanced correction capability only when double-bit errors are detected.
2Reliability
If DEC-TED circuitry is utilized to correct single errors, then error correction capability is improved, but time delay increases
Solution Approach 1:
By segmenting the correction process into SEC and DEC paths, the system can process single-bit errors through the faster SEC path, avoiding the longer processing time required by full DEC-TED circuitry.
Solution Approach 2:
The system applies partial correction (SEC) when sufficient for the error type, rather than always applying the more comprehensive but slower DEC-TED correction process. This partial action reduces time delay while maintaining adequate correction capability.
3Speed
If pure combinational circuits are used for error correction, then correction speed is improved, but power consumption increases
Solution Approach 1:
The system uses periodic clock signals to control the sequential operation of flip-flops and logic gates, enabling error correction to occur in controlled cycles rather than continuous operation, thereby reducing dynamic power consumption while maintaining correction speed.
Solution Approach 2:
The system dynamically activates only the necessary correction circuits based on error detection results. This dynamic switching between active and inactive states reduces power consumption compared to continuously active pure combinational circuits.
Data Source
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AI summary
Error detection and correction decoding apparatus performs single error correction-double error detection (SEC-DED) or double error correction-triple error detection (DEC-TED) depending on whether the data input contains a single-bit error or a multiple-bit error, to reduce power consumption and latency in case of single-bit errors and to provide powerful error correction in case of multiple-bit errors.