Low Power Design Verification via RTL Netlist Analysis
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Solution Overview
Problem
Conventional methodologies for verifying power specifications in low power designs are complex, incomplete, and time-consuming, as they fail to effectively verify low power logic and often result in incorrect verification results due to the integration of low power logic with normal operation logic, leading to tedious manual constraint application and potential exclusion of valid functional modes.
Innovation Solution
A method and system that utilizes a power specification file to verify the completeness, compatibility, and consistency of power requirements by processing a register-transfer level (RTL) netlist representation and generating a reference low power RTL netlist, enabling equivalence checking between the RTL and gate netlists, and validating the insertion of state retention registers and modeling level shifters and isolation cells as domain anchor points.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional equivalence checking is used without low power logic, then verification is simple, but low power logic cannot be verified
Solution Approach 1:
The verification process is segmented into multiple modes: normal operation mode verification and low power mode verification. Each mode has its own constraint set and verification scope, allowing independent verification of different functional states without interfering with each other.
Solution Approach 2:
The verification system dynamically adapts its behavior based on the verification mode. Constraints are selectively applied or removed depending on whether normal operation or low power mode is being verified, enabling the same verification framework to handle multiple operational states flexibly.
2Use of energy by moving object
If low power logic is integrated with normal operation logic, then power savings are achieved, but verification accuracy deteriorates
Solution Approach 1:
Different verification constraints are applied to different parts of the circuit based on their function. Low power logic elements receive specific constraints for low power mode verification, while normal operation logic receives appropriate constraints for normal mode verification, ensuring accurate verification of each component type in its respective operational context.
Solution Approach 2:
The system performs preliminary identification and classification of low power logic elements during the verification setup phase. This preliminary action enables the verification tool to pre-configure appropriate constraints and verification strategies for low power logic, preventing verification errors during the actual verification process.
3Ease of operation
If manual constraints are applied to disable low power logic, then verification can proceed, but the process becomes tedious and error-prone
Solution Approach 1:
The verification tool automatically identifies low power logic elements and applies appropriate verification constraints without requiring manual intervention. The system self-configures its verification parameters based on the circuit design, eliminating the need for users to manually add constraints and reducing the risk of human error.
Solution Approach 2:
The verification system automatically adjusts verification parameters such as constraint application, mode selection, and validation criteria based on the detected circuit characteristics. This automated parameter adjustment eliminates manual constraint configuration and adapts the verification process to the specific low power design requirements.
4Measurement precision
If multiple pin constraints are applied to verify normal operation mode, then verification accuracy improves, but valid functional modes may be excluded
Solution Approach 1:
The verification system dynamically selects and applies constraints based on the operational mode being verified. For normal operation mode, appropriate constraints are applied to ensure accuracy. For low power mode, different constraints are applied to capture the unique behavior of low power logic, ensuring both modes are verified accurately without excluding valid functional modes.
Solution Approach 2:
The system performs preliminary analysis of the circuit to identify all valid operational modes and their corresponding verification requirements. This preliminary action enables the verification tool to pre-configure mode-specific constraints, ensuring comprehensive coverage of all valid functional modes while maintaining verification accuracy for each mode.
Data Source
AI summary
Method and system for verifying power specifications of a low power design are disclosed. The method includes receiving a register-transfer level (RTL) netlist representation of the low power design, receiving a power specification file for describing power requirements of the low power design and verifying the power specification file in accordance with the RTL netlist representation of the low power design. The method further includes verifying completeness, compatibility, and consistency of power requirements for the low power design.