Low Power Input Gating for Memory Standby
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Solution Overview
Problem
Integrated circuits consume significant power due to toggling of control input pins even when disabled or in standby mode, necessitating a reduction in control input pin power consumption to improve power, performance, and area (PPA) efficiency.
Innovation Solution
The implementation of low power input gating circuitry that includes a chip enable device, latch enable device, latch device, and decoder device, which use a latch enable signal to selectively cutoff toggling of the clock input signal to the control input of memory, reducing power consumption by gating off latches during standby mode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If control input pins remain active during standby mode, then memory operations can be quickly resumed, but power consumption increases significantly
Solution Approach 1:
The patent segments the memory system into active and standby portions by selectively gating control input pins. The latch enable device divides the control input signal path, allowing individual pins to be gated independently based on operation type, thus segmenting power consumption by functional region.
Solution Approach 2:
The patent implements periodic activation of control input pins through the latch enable device. During standby mode, pins are gated off periodically rather than continuously active, with selective activation only when memory operations are required, creating a periodic on-demand activation pattern that reduces average power consumption.
2Reliability
If latch devices are continuously enabled, then control signals are always available, but power consumption increases during idle states
Solution Approach 1:
The latch enable device dynamically adjusts the enabled state of latch devices based on operational requirements. The device transitions between enabled and disabled states according to the latch enable signal, making the system adaptable to varying operational conditions rather than maintaining a static enabled state.
Solution Approach 2:
The latch enable device automatically manages the enabled/disabled state of latch devices based on internal signaling. The device monitors operational conditions and self-regulates power gating without external intervention, enabling automatic power management during idle versus active operational states.
Data Source
AI summary
Various implementations described herein are directed to an integrated circuit for implementing low power input gating. In one implementation, the integrated circuit may include a chip enable device configured to receive and use a clock input signal to toggle a control input of memory based on a chip enable signal. The integrated circuit may include a latch device configured to latch the control input of the memory. The integrated circuit may include a latch enable device coupled between the chip enable device and the latch device. The latch enable device may be configured to receive the clock input signal from the chip enable device and use the clock input signal to gate the latch device based on a latch enable signal so as to selectively cutoff toggling of the clock input signal to the control input of the memory.