Low Power Link State Wake-Up Options
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Solution Overview
Problem
Current interconnect architectures, such as PCIe, face challenges in providing fine-tuned power and performance trade-offs, especially in low power states like L1.2, where devices lack granular control over wake-up times and power modes, leading to inefficiencies in power management and performance optimization.
Innovation Solution
The implementation of mechanisms to convey vendor-specific power-mode selection information and map L1.2 exit time options to power-mode options through Vendor-Defined Messages (VDMs) and Latency Tolerance Reporting (LTR) messages, allowing for multiple wake-up time options and finer power-saving states, enabling more optimized system power management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If devices use low power states like L1.2 to save energy, then power consumption is reduced, but devices lack granular control over wake-up times and power modes, leading to power management inefficiencies
Solution Approach 1:
The patent applies parameter changes by introducing multiple wake-up time options (immediate wake-up, first wake-up time, second wake-up time) and mapping them to different power modes. The system can dynamically adjust wake-up time parameters and power mode parameters based on system needs, transforming the fixed power state parameters into adjustable variables that enable fine-grained power management while maintaining energy efficiency.
2Reliability
If current interconnect architectures are used, then device connectivity is established, but fine-tuned power and performance trade-offs cannot be achieved
Solution Approach 1:
The patent implements dynamics by enabling dynamic selection among multiple wake-up time options and power modes. The system can transition between different power states (L1.2, L1.3, L2.0, etc.) with different wake-up time characteristics based on real-time system requirements. This dynamic adaptability allows the interconnect architecture to optimize both power consumption and performance responsiveness, resolving the contradiction between reliable connectivity and adaptability.
3Loss of energy
If devices enter low power states with fixed wake-up times, then power savings are achieved, but performance optimization is limited due to lack of granular control
Solution Approach 1:
The patent applies segmentation by dividing the power management functionality into distinct segments: multiple wake-up time options (immediate, first wake-up time, second wake-up time), multiple power modes (L1.2, L1.3, L2.0, etc.), and separate control mechanisms for each segment. This segmentation allows the system to select the appropriate combination of wake-up time and power mode for specific performance requirements, enabling fine-grained optimization of both power savings and performance without compromising either aspect.
Data Source
AI summary
Systems and devices can include a power management controller to determine a low power mode exit timing from a plurality of low power mode exit timing options, and cause the setting of a low power mode control register based on the determined low power mode exit timing. A message generator can generate a power mode request message. The power mode request message indicating the determined low power mode exiting timing. The power mode request message can be transmitted to a host across a multilane link.