Low Power Scan Flip-Flop Cells for IC Testing
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Solution Overview
Problem
Integrated circuits (ICs) face high power consumption during scan testing due to all flip-flop cells and combinational logic toggling simultaneously, exceeding the IC's power rating, especially as chip density and speed increase, necessitating a low power scan system.
Innovation Solution
The implementation of a low power scan system using flip-flop cells with a master latch, slave latch, and multiplexers that receive a clock signal gated by an input trigger signal, allowing selective activation of flip-flop cells in a round-robin manner to reduce power dissipation, and configuring every N flip-flop cells as subsets to bypass non-selected slave latches during scan testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If all flip-flop cells are activated during scan testing, then complete coverage of internal nodes is achieved, but power consumption exceeds the IC's power rating
Solution Approach 1:
The patent divides the scan chain into multiple segments or groups of flip-flop cells. Instead of activating all flip-flop cells simultaneously, only one segment is activated at a time during scan testing. This segmentation approach maintains complete test coverage over multiple cycles while limiting instantaneous power consumption to levels below the IC's power rating.
Solution Approach 2:
The patent implements periodic activation of different flip-flop cell segments across multiple clock cycles. Each segment is activated in turn during designated time periods, ensuring that all internal nodes are eventually tested while distributing the power consumption over time rather than concentrating it in a single moment.
2Productivity
If chip density and speed are increased, then IC performance is improved, but scan shift power consumption is exacerbated
Solution Approach 1:
The patent segments the high-density flip-flop cells into multiple groups, allowing the IC to leverage high chip density for improved performance while managing scan shift power by activating only a subset of cells at any given time. This enables the system to benefit from increased chip density without proportionally increasing instantaneous scan power consumption.
3Reliability
If scan testing is performed on high-density ICs, then comprehensive defect detection is achieved, but power consumption exceeds operational limits
Solution Approach 1:
The patent employs periodic activation of flip-flop cell segments during scan testing. By cycling through different segments across multiple test cycles, the system achieves comprehensive defect detection capability while ensuring that power dissipation at any instant remains within operational limits, preventing harmful thermal effects.
Data Source
AI summary
An integrated circuit operable in a scan mode includes a scan chain formed by cascaded flip-flop cells. Each flip-flop cell includes a master latch that receives a first data signal and generates a first latch signal, a slave latch that receives the first latch signal and generates a second latch signal, and a multiplexer having first and second inputs respectively connected to the master and slave latches that receives a first input signal and the second latch signal, and generates a scan data output signal depending on an input trigger signal. The first input signal is one of the first data signal and the first latch signal. The clock signal provided to the slave latch is gated by the input trigger signal.