Low Power Sensor Chip Architecture for Dynamic Clock Rate Management
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Solution Overview
Problem
Current computing devices face challenges in managing power consumption of multiple sensors effectively, especially in low power states, which limits their functionality and battery life.
Innovation Solution
A method for managing processor analysis of multiple sensors by monitoring and comparing sensor signals with predetermined signatures, utilizing a low power core to reduce power consumption while maintaining sensor functionality, and partitioning functions among processors to optimize power usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If computing devices enter a low power state to conserve battery power, then power consumption is reduced, but device capability and sensor functionality are limited
Solution Approach 1:
The patent divides the processor into multiple cores with different power consumption characteristics: a low power core and one or more high performance cores. The low power core can independently monitor sensor signals and perform basic analysis at reduced power consumption, while high performance cores remain in sleep mode or are activated only when complex processing is needed. This segmentation allows the device to maintain essential sensor functionality in low power state while preserving the capability to perform complex sensor analysis when required.
2Measurement precision
If multiple sensors are monitored and analyzed continuously, then sensor accuracy and availability are maintained, but power consumption increases
Solution Approach 1:
The patent implements dynamic power management where the processing power allocated to sensor analysis changes based on system state. The low power core continuously monitors sensor signals at basic levels, and the system dynamically transitions to high performance cores when complex analysis is required. This dynamic adjustment of processing resources maintains sensor accuracy and availability while optimizing power consumption by using minimal resources during normal operation and scaling up only when necessary.
Data Source
AI summary
A method, device, system, or article of manufacture is provided for low-power management of multiple sensor chip architecture. In one embodiment, a method comprises, at a computing device that includes a first processor, a second processor and a third processor, receiving, by the first processor operating at a first clock rate, first sensor data from a first sensor operating at a first data rate; determining, by the first processor, a movement of the computing device using the first sensor data; in response to determining the movement of the computing device, performing, by the first processor, a first motion state algorithm to determine whether a modality of the computing device is a first motion state; and, in response to determining that the modality of the computing device is not the first motion state, changing, by the first processor, at least one of the first processor to operate at a second clock rate sufficient to perform a second motion state algorithm and changing the first sensor to operate at a second data rate sufficient to perform the second motion state algorithm, wherein the second motion state algorithm is used to determine whether the modality of the computing device is a second motion state.