Automated Low-Power Sequential Circuitry Selection via Clock Activity Simulation
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Solution Overview
Problem
Integrated circuits face challenges in reducing clock tree switching power consumption, as existing low-power sequential circuitry tends to be slower and larger, making it difficult for automated design tools to introduce these cells into circuit designs while meeting timing and area optimization constraints.
Innovation Solution
The approach involves simulating circuit designs to identify high-average clock switching activity portions, replacing sequential circuit elements with low-power sequential circuitry such as multibit flip-flops or low-clock pin capacitance flip-flops, and potentially switching back to higher-power cells based on further analysis to meet timing and power constraints.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If low-power sequential circuitry is used, then power consumption is reduced, but timing performance deteriorates
Solution Approach 1:
The patent applies local quality by selectively replacing sequential circuit elements with low-power alternatives only in specific portions of the clock tree where the clock signal is gated for significant portions of time. High-activity portions continue to use standard sequential circuitry to maintain timing performance, while low-activity portions use low-power cells to reduce power consumption. This localized application resolves the contradiction by optimizing power savings only where timing constraints allow.
Solution Approach 2:
The patent implements dynamics by using simulation to dynamically identify which sequential circuit elements should be replaced with low-power alternatives based on actual clock gating behavior. The selection of low-power cells is not static but determined through simulation analysis of clock activity patterns, allowing the design to adaptively optimize power consumption while maintaining timing performance in critical paths.
2Loss of energy
If low-power sequential circuitry is used, then power consumption is reduced, but circuit area increases
Solution Approach 1:
The patent resolves this contradiction by applying low-power sequential circuitry locally only to portions of the design where clock gating occurs frequently. By limiting the scope of low-power cell deployment to specific low-activity regions rather than applying it universally, the patent achieves power savings while minimizing the additional area overhead to only those regions where it provides benefit.
3Speed
If automated design tools optimize timing and area, then timing performance improves, but power consumption increases
Solution Approach 1:
The patent applies preliminary action by performing simulation analysis before finalizing the design to identify which sequential circuit elements are good candidates for low-power replacement. By pre-identifying low-activity portions through simulation of clock gating behavior, the patent enables automated design tools to make informed decisions about where to apply low-power optimizations without compromising timing or area optimization goals.
Solution Approach 2:
The patent implements feedback by using simulation results to inform the selection of sequential circuit elements for low-power optimization. The simulation provides feedback about actual clock activity patterns, which then guides the automated design tools to selectively replace only those elements that will benefit from low-power implementation, creating a closed-loop optimization process that balances timing, area, and power.
Data Source
AI summary
Techniques are disclosed relating to reducing dynamic power consumption in integrated circuits. In some embodiments, simulation is performed at one or more stages of a circuit design to identify portions of the circuit with relatively high average clock switching activity, based on an amount of clock gating during the simulation by one or more clock gaters. In some embodiments, sequential circuit elements in the identified portions are specified as candidates for implementation using low-power sequential circuitry. Examples of low-power sequential circuitry include multibit flip flops and flip flops with low clock pin input capacitance. The disclosed techniques may allow automated design tools to significantly reduce dynamic power consumption while still meeting other design parameters such as timing constraints.