Low-Power SRAM Cell for In-Memory Computing
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Solution Overview
Problem
In-memory computing units based on SRAM face challenges in balancing output accuracy and energy consumption during two-bit by two-bit multiplication operations, with traditional analog methods requiring high energy and having fixed accuracy levels, while digital methods are inefficient due to multiple clock cycles required for calculations.
Innovation Solution
A low-power SRAM memory cell design with five word lines and four bit lines is introduced, where the word line controlling the bit line is combined with input data, allowing for reduced voltage swing and efficient two-bit by two-bit multiplication, enabling scalable precision and reduced energy consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If analog-to-digital conversion is used for in-memory computing multiplication, then multi-bit multiplication can be performed, but energy consumption increases and output accuracy is limited to fixed levels
Solution Approach 1:
The patent segments the multiplication operation into multiple single-bit multiplication steps, where each bit cell performs a simple single-bit multiplication and the results are accumulated through sequential addition. This breaks down the complex analog-to-digital conversion process into simpler, lower-power digital operations that can be performed iteratively
Solution Approach 2:
The patent employs periodic clock cycles to perform sequential single-bit multiplications and accumulations. Each clock cycle handles one bit position, with intermediate results stored in registers for the next cycle. This periodic digital approach replaces continuous analog conversion, reducing peak power consumption while maintaining multi-bit multiplication capability
2Adaptability or versatility
If analog-to-digital conversion is used for in-memory computing multiplication, then multi-bit multiplication can be performed, but the conversion process increases system complexity
Solution Approach 1:
The patent extracts and removes the analog-to-digital converter component from the in-memory computing system. Instead of performing analog multiplication followed by ADC conversion, the system directly performs digital multiplication operations at the bit cell level, eliminating the need for complex ADC circuitry and associated calibration requirements
Solution Approach 2:
The patent substitutes the analog electrical system with a digital logical system. Rather than using analog voltage levels to represent multiplication results, the system uses digital logic operations (AND gates for single-bit multiplication, adders for accumulation) to compute multi-bit products, replacing the continuous analog domain with discrete digital domains
3Use of energy by moving object
If digital multiplication is performed in bit cell array, then energy consumption is reduced, but multiple clock cycles are required for calculation
Solution Approach 1:
The patent performs preliminary preparation of operand data before the multiplication process, organizing the multi-bit numbers into aligned bit positions within the bit cell array. This pre-positioning allows the sequential single-bit multiplications to proceed efficiently without additional data movement delays during the calculation phase
Solution Approach 2:
The patent maintains continuous useful action by overlapping operations across clock cycles. While one set of bit cells performs multiplication in the current cycle, other bit cells are preparing for the next operation, and accumulation results are being registered for subsequent addition. This pipelined approach ensures that the system remains productive throughout the multi-cycle multiplication process
4Use of energy by moving object
If word line controlling bit line is combined with input data, then voltage swing is reduced and energy consumption decreases, but circuit design complexity increases
Solution Approach 1:
The patent merges the word line control signal with the input data signal by using the input data bits to directly control the activation of bit cells through the word line. Instead of separate control and data paths, the data bits themselves determine which bit cells are activated and what operations they perform, reducing the need for additional control circuitry and minimizing voltage swing on control lines
Data Source
AI summary
A low-power SRAM memory cell includes five word lines and four bit lines. The five word lines are a first word line, a second word line, a third word line, a fourth word line and a fifth word line. The four bit lines are a first bit line, a second bit line, a third bit line, and a fourth bit line. During the operation process of calculating a binary 10×11, the first word line is 1, the second word line is 0, the third word line is 0, the fourth word line is 1, the high bit stored in the bit cell is 1, and the low bit is 1. The voltage value of the fifth word line is 0.73 volt. At this time, the first bit line, the second bit line, and the third bit line do not discharge, while the fourth bit line discharges.