Low Pressure Bake for Semiconductor Surface Cleaning

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Solution Overview

Problem

The semiconductor industry faces challenges in maintaining the purity of substrate surfaces and preventing reoxidation during epitaxial deposition, which affects the quality and throughput of silicon devices, especially in single-wafer processing where processing time is critical.

Innovation Solution

A method involving a low pressure bake in a chemical vapor deposition (CVD) chamber, where the pressure is reduced to between 1×10−6 Torr and 10 Torr, and a reducing gas is introduced to remove impurities and prevent oxide growth, followed by a rapid increase in pressure for deposition, using a system with a reinforced reaction chamber and a robot for substrate handling.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If wafers are cleaned with APM and HF treatments to remove native oxide and contaminants, then the substrate surface purity is improved, but the thermal budget is consumed and reoxidation occurs during storage time

Engineering Contradiction:
Improvesubstrate surface purityVSAvoidstorage time before deposition
Core Design Contradiction:
Manufacturing precisionVSLoss of time

Solution Approach 1:

The patent performs the oxide removal and surface cleaning action immediately before deposition by conducting a low pressure bake that reduces oxide growth and removes contaminants in-situ within the vacuum chamber, eliminating the storage time gap where reoxidation would occur

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent uses a vacuum environment (low pressure bake chamber) as an inert atmosphere that prevents oxidation during the cleaning and pre-deposition treatment, allowing the substrate surface to remain oxide-free from cleaning through deposition without exposure to ambient air

Inventive Principle:
Principle #39Inert atmosphere (Inert environment)

2Manufacturing precision

If single wafer processing is used to improve temperature and gas flow distribution control, then manufacturing precision is improved, but processing time increases due to serial processing

Engineering Contradiction:
Improvetemperature and gas flow distribution controlVSAvoidwafer throughput
Core Design Contradiction:
Manufacturing precisionVSProductivity

Solution Approach 1:

The patent changes the pressure parameter to a low pressure environment (10^-3 to 10^-6 Torr) during the bake and deposition process, which enables faster processing rates and improved surface quality, thereby increasing throughput while maintaining the precision benefits of single-wafer processing

Inventive Principle:
Principle #35Parameter changes

3Manufacturing precision

If low pressure bake is performed to remove impurities and prevent oxide growth, then substrate surface purity is improved, but processing time is added to the sequence

Engineering Contradiction:
Improvesubstrate surface purityVSAvoidprocessing time
Core Design Contradiction:
Manufacturing precisionVSLoss of time

Solution Approach 1:

The patent merges the low pressure bake, oxide removal, and deposition preparation steps into a single integrated process sequence that occurs in-situ within the vacuum chamber, eliminating the need for separate cleaning and storage steps that would consume additional time

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively cleans the substrate surface, maintains oxide-free conditions, and improves wafer throughput without exhausting the thermal budget, ensuring high-quality epitaxial layers and reducing fabrication costs.

Implementation Method 1

introducing a reducing gas to the reaction chamber... to remove impurities and prevent oxide growth

Methodology Applied
Scientific EffectChemical reduction: Reduction

Implementation Method 2

depositing a layer by chemical vapor deposition at the deposition pressure

Methodology Applied
Scientific EffectChemical vapor deposition: Chemical Vapour Deposition

Data Source

PatentUS7871937B2Process and apparatus for treating wafers
Publication Date: 2011.01.18 ASM IP HLDG BV
  • US7871937B2 patent drawing
  • US7871937B2 patent drawing
  • US7871937B2 patent drawing

AI summary

Methods and systems are provided for low pressure baking to remove impurities from a semiconductor surface prior to deposition. Advantageously, the short, low temperature processes consume only a small portion of the thermal budget, while still proving effective at removing interfacial oxygen from the semiconductor surface. The methods and systems are particularly well suited for treating semiconductor surfaces before epitaxy.