Low-Rank Matrix Compression Hardware for AI Memory Bottlenecks

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing compression techniques for AI workloads involving large matrices and tensors are insufficient to address the significant storage, bandwidth, and power requirements, leading to high costs.

Innovation Solution

Implement low-rank decomposition-based hardware compression methods for matrices and tensors, utilizing graphics processing units (GPUs) to optimize storage and processing efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If existing compression techniques are used for AI workloads, then some cost reduction is achieved, but storage, bandwidth, and power requirements remain significantly high

Engineering Contradiction:
Improvepower consumptionVSAvoidstorage capacity
Core Design Contradiction:
Loss of energyVSQuantity of substance

Solution Approach 1:

The patent applies segmentation by dividing large matrices and tensors into smaller blocks that can be independently compressed using low-rank decomposition. Each block is processed separately, allowing for more efficient storage and retrieval while reducing overall memory bandwidth requirements and power consumption during AI operations.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent changes the fundamental parameter representation of matrices by transforming them into low-rank decomposed forms (e.g., using SVD or other decomposition methods). This parameter transformation reduces the storage capacity needed while enabling efficient reconstruction and computation, directly addressing both storage and power consumption issues.

Inventive Principle:
Principle #35Parameter changes

2Loss of energy

If existing compression techniques are used for AI workloads, then some cost reduction is achieved, but bandwidth requirements remain significantly high

Engineering Contradiction:
Improvepower consumptionVSAvoidbandwidth
Core Design Contradiction:
Loss of energyVSSpeed

Solution Approach 1:

The patent applies preliminary action by pre-computing and storing the decomposition factors of matrices in a compressed format before they are needed for AI operations. This pre-processing step reduces the bandwidth requirements during actual inference or training, as the system only needs to retrieve and reconstruct the decomposed forms rather than handling full-size matrices.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent transitions from storing matrices in their original high-dimensional form to storing them in a lower-dimensional decomposed form. This dimensional reduction allows for more efficient memory bandwidth utilization while maintaining the ability to reconstruct and use the data for AI computations.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Loss of energy

If existing compression techniques are used for AI workloads, then some cost reduction is achieved, but processing efficiency is compromised

Engineering Contradiction:
Improvepower consumptionVSAvoidprocessing efficiency
Core Design Contradiction:
Loss of energyVSProductivity

Solution Approach 1:

The patent introduces an intermediary decomposed representation of matrices that serves as a bridge between storage efficiency and processing efficiency. The low-rank decomposed form acts as an intermediary that can be efficiently stored and transmitted while enabling fast reconstruction and computation through optimized algorithms, thus maintaining processing efficiency while reducing power consumption.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS20250293706A1Low-rank decomposition-based hardware compression of matrices and tensors
Publication Date: 2025.09.18 INTEL CORP
  • US20250293706A1 patent drawing
  • US20250293706A1 patent drawing
  • US20250293706A1 patent drawing

AI summary

Low-rank decomposition-based hardware compression of matrices and tensors is described. An example of an apparatus includes a computer memory to store data for processing, and one or more processing resources including one or more accelerators, the one or more accelerators including circuitry for processing of one or more matrices. The circuitry includes decomposition-based compression circuitry, the decomposition-based compression circuitry performing decomposition of one or more input matrices to generate components representing approximated versions of the one or more input matrices.