Self-Aligned Low Resistance Contact Layer Formation
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Solution Overview
Problem
Conventional methods for forming self-aligned low resistance contact layers in semiconductor devices face issues with non-uniformity due to implant profile variations, leading to resistivity issues and high junction leakage, which can be exacerbated by the need for multiple thermal cycles that cause dopant deactivation and diffusion.
Innovation Solution
A method involving selective deposition of an amorphous semiconductor layer using alternating precursors in a PECVD process at low temperature, followed by metal layer deposition and annealing to form uniform silicide or germanide layers on source and drain regions, minimizing doping diffusion and controlling layer thickness and profile.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If implant-based pre-amorphization is used to create amorphous silicon regions, then self-aligned salicide formation is achieved, but non-uniform implant profile causes non-uniform salicide thickness and resistivity
Solution Approach 1:
The patent changes the deposition method from implant-based to PECVD-based amorphous silicon deposition. By controlling deposition parameters (temperature <400°C, alternating precursors), uniform amorphous silicon layers are formed on source and drain regions, which then react with metal to form uniform salicide layers with controlled thickness and resistivity.
Solution Approach 2:
The patent replaces the mechanical implantation process with a chemical vapor deposition process. Instead of using neutral species implants to create amorphous regions, PECVD is used to deposit amorphous silicon layers, eliminating the non-uniformity inherent in implant profiles while achieving the same self-aligned salicide formation effect.
2Manufacturing precision
If two step annealing process is used to rectify implant profile problems, then salicide uniformity is improved, but number of thermal cycles increases causing dopant deactivation and diffusion
Solution Approach 1:
The patent performs the amorphous silicon deposition step before metal layer deposition, creating a uniform sacrificial layer that controls salicide thickness. This preliminary action eliminates the need for subsequent annealing steps to correct non-uniformity, thereby avoiding dopant deactivation and diffusion that would result from multiple thermal cycles.
3Area of stationary object
If metal layer is blanket deposited on substrate, then complete coverage is achieved, but excessive consumption by metal layer causes substrate recessing and high junction leakage
Solution Approach 1:
The patent uses PECVD to selectively deposit amorphous silicon only on the source and drain regions where salicide formation is desired. This localized deposition ensures complete coverage of the target areas while preventing metal layer consumption in other regions, thereby avoiding substrate recessing and junction leakage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of self-aligned low resistance contact layers with uniform thickness and profile, reducing resistivity and junction leakage while minimizing thermal cycles and dopant deactivation.
Implementation Method 1
An amorphous semiconductor layer is selectively deposited onto each of the source and drain regions by alternatingly exposing the substrate to a first precursor and a second precursor in a plasma enhanced chemical vapor deposition (PECVD) process
Implementation Method 2
an annealing process is performed on the substrate to allow the metal layer to react with the amorphous semiconductor layer formed on each of the source and drain regions to form a low resistance contact layer
Data Source
AI summary
Embodiments of the present invention describe a method of fabricating low resistance contact layers on a semiconductor device. The semiconductor device comprises a substrate having source and drain regions. The substrate is alternatingly exposed to a first precursor and a second precursor to selectively deposit an amorphous semiconductor layer onto each of the source and drain regions. A metal layer is then deposited over the amorphous semiconductor layer on each of the source and drain regions. An annealing process is then performed on the substrate to allow the metal layer to react with amorphous semiconductor layer to form a low resistance contact layer on each of the source and drain regions. The low resistance contact layer on each of the source and drain regions can be formed as either a silicide layer or germanide layer depending on the type of precursors used.