Low Dielectric Oxide and Low Resistance OP Stack for 3D NAND
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Solution Overview
Problem
Existing 3D memory cell manufacturing techniques face challenges in achieving low dielectric constant and reduced resistivity, particularly with oxide and polysilicon materials, which affect the performance and capacity of memory devices like NAND flash memory.
Innovation Solution
The use of precursors such as octamethylcyclotetrasiloxane (OMCTS) and germane in PECVD processes to treat oxide and polysilicon materials, combined with plasma treatment, to reduce the dielectric constant of oxide layers and lower the resistivity of polysilicon layers, forming OP stacks with improved properties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional oxide materials are used in 3D memory cell manufacturing, then the dielectric constant is high, but this leads to increased RC delay and reduced device performance
Solution Approach 1:
The patent changes the chemical composition parameters of the oxide material by incorporating carbon-containing precursors (such as OMDs, OMTS, or HMDSO) during PECVD processing. This modifies the dielectric constant of the oxide layer from conventional high values to lower values, directly reducing RC delay while maintaining the insulating function of the oxide layer in the OP stack structure
Solution Approach 2:
The patent creates a composite oxide material system that combines silicon oxide with carbon-containing compounds deposited from precursors like OMDs, OMTS, or HMDSO. This composite structure achieves both low dielectric constant properties and adequate insulation performance, resolving the contradiction between low RC delay and sufficient dielectric function
2Reliability
If conventional polysilicon materials are used, then the resistivity is high, but this limits the conductivity required for optimal memory cell operation
Solution Approach 1:
The patent changes the physical and chemical parameters of polysilicon by controlling deposition conditions (temperature, pressure, precursor ratios) during PECVD processing. These parameter changes produce polysilicon with modified crystalline structure and lower resistivity, enabling optimal conductivity for memory cell operation while maintaining the polysilicon layer's function in the OP stack
3Quantity of substance
If 3D memory cells are manufactured with smaller geometries to increase capacity, then device capacity increases, but manufacturing precision requirements increase
Solution Approach 1:
The patent utilizes PECVD process parameters (temperature, pressure, gas flow rates, precursor composition) to achieve precise control over film thickness, composition, and uniformity. This enables manufacturing of smaller geometry 3D memory cells with the required geometric precision, as the PECVD process can deposit conformal films with controlled stoichiometry and minimal variation across complex 3D structures
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in memory devices with reduced dielectric constant and resistivity, enhancing device performance and capacity while allowing for smaller geometries and lower costs, thereby addressing the limitations of current 3D memory cell manufacturing.
Implementation Method 1
introducing octamethylcyclotetrasiloxane precursor to the PECVD chamber to deposit a silicon oxide layer over the substrate, and depositing a polysilicon layer over the silicon oxide layer
Implementation Method 2
introducing a silicon precursor and germane to the PECVD chamber to form a SixGe(1-x) film over the silicon oxide layer
Implementation Method 3
a plasma treatment process is used to nitridate the interface between layers of the OP stack
Data Source
AI summary
Embodiments described herein generally relate to methods of manufacturing an oxide/polysilicon (OP) stack of a 3D memory cell for memory devices, such as NAND devices. The methods generally include treatment of the oxide and/or polysilicon materials with precursors during PECVD processes to lower the dielectric constant of the oxide and reduce the resistivity of the polysilicon. In one embodiment, the oxide material is treated with octamethylcyclotetrasiloxane (OMCTS) precursor. In another embodiment, germane (GeH4) is introduced to a PECVD process to form SixGe(1-x) films with dopant. In yet another embodiment, a plasma treatment process is used to nitridate the interface between layers of the OP stack. The precursors and plasma treatment may be used alone or in any combination to produce OP stacks with low dielectric constant oxide and low resistivity polysilicon.