Low Resistance Power Switching Device with 3D Stacked MOSFETs
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Solution Overview
Problem
High-power applications require low on-state resistance and high current carrying capacity, which individual transistor elements cannot meet, necessitating the connection of numerous transistors in parallel to reduce aggregate resistance and increase current capability, while minimizing interconnection resistance in power switching devices.
Innovation Solution
The power switching device employs multiple MOSFETs connected in parallel with conductive pathways formed in successive metallization layers, using vias to connect gates, sources, and drains, and presenting external terminals with large, shared conductive areas to reduce terminal resistance by increasing cross-sectional area and shortening conductive pathways.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If multiple transistors are connected in parallel to reduce aggregate resistance and increase current capability, then the on-state resistance decreases and current carrying capacity increases, but the interconnection resistance and device complexity increase
Solution Approach 1:
The patent transitions from planar 2D interconnection to 3D vertical stacking, where multiple transistor layers are connected through vias and conductive pathways in the vertical dimension. This allows parallel connection of numerous transistors while maintaining low interconnection resistance by providing direct vertical pathways between layers, thus reducing aggregate on-state resistance without proportionally increasing device complexity
Solution Approach 2:
The patent implements nested interconnection structures where conductive pathways and vias are embedded within insulating layers, and multiple transistor layers are stacked within a single device structure. This nesting approach consolidates numerous interconnections into a compact 3D architecture, reducing the overall interconnection resistance while managing device complexity through integrated multi-layer design
2Quantity of substance
If numerous transistors are connected in parallel to meet high-power requirements, then current carrying capacity increases, but the interconnection resistance becomes significant
Solution Approach 1:
By stacking transistor layers vertically and connecting them through conductive vias, the patent enables parallel connection of numerous transistors (increasing quantity) while the vertical conductive pathways provide low-resistance interconnection. This 3D architecture allows current to flow through multiple parallel pathways simultaneously, increasing current carrying capacity while keeping interconnection resistance minimal compared to planar configurations
Solution Approach 2:
The patent divides the device into multiple discrete transistor layers separated by insulating layers, with each layer containing numerous transistor elements. This segmentation allows independent optimization of each layer while the collective parallel operation of all layers achieves high current carrying capacity. The conductive pathways segment the current flow into multiple parallel channels, reducing overall interconnection resistance
Data Source
AI summary
A semiconductor device includes a semiconductor substrate with doped regions of a first type and doped regions of a second type. A first metallization layer connects to the doped regions of the first type through conductive paths, such that current is able to flow within the metallization layer along a plurality of linear axes. A second metallization layer connects to the doped regions of the second type through conductive paths, such that that current is able to flow within the metallization layer along a plurality of linear axes. Contacts on an exterior surface of the semiconductor device can be arranged concentrically.