Low Resistive Source and Drain Regions in Replacement Metal Gate Process
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Solution Overview
Problem
Conventional MOSFET processing, including the replacement gate scheme, results in diffused source and drain junctions, leading to increased resistance and degraded short-channel control, which hampers device performance and is exacerbated by pitch scaling issues.
Innovation Solution
A method involving the formation of a semiconductor structure with low resistive source and drain regions by using a sacrificial gate process, where a sacrificial gate region with spacers is formed, followed by planarizing dielectric material deposition and removal to expose the semiconductor substrate, allowing for dopant outdiffusion and subsequent formation of high k gate dielectric and metal gate structures, thereby creating sharp, low-resistance junctions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If ion implantation followed by activation anneal is used to form source and drain regions, then the source and drain regions can be formed, but the junctions become diffused leading to increased resistance and degraded short-channel control
Solution Approach 1:
The patent forms the source and drain regions by outdiffusion of dopant from the doped semiconductor layer before the gate stack is formed. This preliminary formation of sharp junctions avoids subsequent diffusion that would occur with conventional ion implantation and activation anneal, thereby maintaining junction sharpness and short-channel control throughout the remaining processing steps.
2Adaptability or versatility
If high energy source and drain implants are used to address pitch scaling, then pitch scaling challenges can be addressed, but the junction diffusion and resistance issues are worsened
Solution Approach 1:
The patent performs the dopant outdiffusion to form source and drain regions at an early stage before pitch scaling becomes critical. By establishing the doped semiconductor layer with controlled dopant distribution early in the process, the method enables subsequent pitch scaling without requiring high energy implants that would degrade junction sharpness.
3Ease of manufacture
If conventional ion implantation is used to form source and drain regions, then the regions can be formed, but the resistance increases due to diffused junctions
Solution Approach 1:
The patent replaces the mechanical ion implantation process with a thermal diffusion process where dopant atoms naturally diffuse out from the doped semiconductor layer into the semiconductor substrate during annealing. This substitution eliminates the need for high energy ion bombardment while achieving effective source and drain region formation with sharper junctions and lower resistance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in sharp, low-resistance source and drain regions, improving device performance and addressing pitch scaling challenges by minimizing dopant diffusion and enhancing short-channel control.
Implementation Method 1
an anneal is performed that causes outdiffusion of dopant from remaining portions of the doped semiconductor layer forming a source region and a drain region
Data Source
AI summary
In one embodiment a method is provided that includes providing a structure including a semiconductor substrate having at least one device region located therein, and a doped semiconductor layer located on an upper surface of the semiconductor substrate in the at least one device region. After providing the structure, a sacrificial gate region having a spacer located on sidewalls thereof is formed on an upper surface of the doped semiconductor layer. A planarizing dielectric material is then formed and the sacrificial gate region is removed to form an opening that exposes a portion of the doped semiconductor layer. The opening is extended to an upper surface of the semiconductor substrate and then an anneal is performed that causes outdiffusion of dopant from remaining portions of the doped semiconductor layer forming a source region and a drain region in portions of the semiconductor substrate that are located beneath the remaining portions of the doped semiconductor layer. A high k gate dielectric and a metal gate are then formed into the extended opening.