Low Resolution ADC for Phased Array Power Reduction
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Solution Overview
Problem
The high power consumption of analog-to-digital converters in digital beamforming architectures for large phased array receivers poses a significant impediment to implementing digital beamforming in large phased array systems, as each antenna requires a separate converter, leading to prohibitive total power consumption.
Innovation Solution
The use of low resolution analog-to-digital converters, such as one-bit or two-bit converters, which compare analog inputs to a reference value primarily triggered by dominant noise values rather than signal values, eliminating the need for variable gain amplifiers and feedback loops, thereby reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If high resolution analog-to-digital converters are used in digital beamforming architecture, then signal conversion accuracy is improved, but power consumption increases prohibitively
Solution Approach 1:
The patent employs low-resolution (1-bit or 2-bit) analog-to-digital converters instead of high-resolution converters. These simplified converters consume significantly less power while the system compensates for reduced individual converter precision through digital signal processing and array processing techniques, achieving acceptable overall signal conversion accuracy at much lower power consumption
Solution Approach 2:
The patent changes the resolution parameter of the analog-to-digital converters from high (typically 8-16 bits) to low (1-2 bits). This parameter change dramatically reduces power consumption while maintaining functional effectiveness through the use of multiple antennas and digital beamforming algorithms that process the lower-resolution signals collectively
2Measurement precision
If variable gain amplifiers and feedback loops are implemented, then signal quality is improved, but device complexity and power consumption increase
Solution Approach 1:
The patent extracts and removes variable gain amplifiers and feedback loops from the signal processing chain. Instead of using these complex analog components to maintain signal quality, the system relies on digital signal processing after low-resolution conversion, significantly simplifying the device architecture while maintaining adequate signal quality through post-processing
Solution Approach 2:
The patent replaces complex analog signal processing mechanisms (variable gain amplifiers and feedback loops) with digital processing approaches. The transition from analog to digital domain allows for simpler conversion hardware with the complexity shifted to programmable digital algorithms, reducing overall device complexity and power consumption
Data Source
AI summary
A wireless receiver is disclosed. The wireless receiver includes a phased array antenna panel having a plurality of antennas, and a low resolution analog-to-digital (A/D) converter coupled to each of the plurality of antennas, where the low resolution A/D converter is configured to provide a digital output based on comparing a reference value with a sum of noise value and signal value of an analog input received by the corresponding one of the plurality of antennas. Noise signals received by the plurality of antennas are uncorrelated, and a signal to noise ratio (SNR) of the analog input can be less than one. The low resolution A/D converter can be a one-bit A/D converter. The one-bit A/D converter can be a comparator receiving the sum of noise value and signal value as one comparator input, and receiving the reference value as another comparator input.