Low-Side FET Gate Boosting for Lower Converter On-Resistance
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Solution Overview
Problem
Conduction loss in switch-mode power converters is significant due to the on-resistance (RDS_ON) of the switches, which is influenced by the W/L ratio of the FETs and limited by the input voltage, leading to inefficiencies and increased parasitic capacitance.
Innovation Solution
The proposed solution involves a controller-driven method that utilizes the voltage overshoot during the switching process to increase the gate-source voltage of the low side FET, reducing its RDS_ON and conduction loss. This is achieved by coupling a capacitor and switches between the power terminal and the FET control terminal, allowing energy from parasitic inductance to be recycled and used to elevate the gate voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the W/L ratio of FETs is increased to reduce on-resistance, then conduction loss decreases, but parasitic capacitance increases
Solution Approach 1:
The patent changes the voltage parameter by utilizing voltage overshoot during switching transitions to dynamically enhance the gate-source voltage of the low side FET. This allows the FET to operate with effectively lower on-resistance during critical periods without permanently increasing the W/L ratio, thereby reducing conduction loss while avoiding the parasitic capacitance penalty associated with larger device dimensions.
2Loss of energy
If the gate-source voltage is increased to reduce on-resistance, then conduction loss decreases, but the device requires higher voltage capability
Solution Approach 1:
The patent applies preliminary action by capturing and storing the voltage overshoot energy that naturally occurs during switching transitions. This stored energy is then applied to enhance the gate-source voltage of the low side FET at the optimal moment, reducing its on-resistance and conduction loss without requiring the device to be designed for continuously higher voltage ratings.
3Loss of energy
If larger FETs are used to reduce on-resistance, then conduction loss decreases, but device area increases
Solution Approach 1:
The patent dynamically changes the electrical parameters (gate voltage) during operation to achieve lower effective on-resistance without physically increasing the FET area. By utilizing voltage overshoot to temporarily enhance gate drive voltage, the low side FET achieves reduced conduction loss while maintaining compact device dimensions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the RDS_ON of the low side FET, thereby decreasing conduction losses and improving the overall efficiency of the power converter without increasing the size of the FETs. The method also allows for the recycling of energy stored in parasitic inductance, reducing waste and enhancing converter performance.
Implementation Method 1
utilizes the voltage overshoot during the switching process to increase the gate-source voltage of the low side FET
Implementation Method 2
allowing energy from parasitic inductance to be recycled and used to elevate the gate voltage
Data Source
AI summary
An apparatus includes a first transistor having a first transistor control terminal and coupled between a power terminal and a switching terminal. The apparatus further includes a second transistor having a second transistor control terminal and coupled between the switching terminal and a ground terminal. The apparatus further includes a first switch coupled between the power terminal and the second transistor control terminal, the first switch having a first switch control terminal; The apparatus further includes a second switch coupled between the second control terminal and the ground terminal, the second switch having a second switch control terminal. The apparatus also includes a controller having a control input, a first control output, and a second control output, the control input coupled to the second transistor control terminal, the first control output coupled to the first switch control terminal, and the second control output coupled to the second switch control terminal.