Low-Skew Phase Generation for Multi-FPGA Signal Multiplexing
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Solution Overview
Problem
Current FPGA prototyping systems face challenges in achieving low skew phase generation for multiplexing signals due to limited global low skew lines, which affects the logical correctness and performance of interconnects between FPGAs, especially as the number of fanout loads increases.
Innovation Solution
A method and apparatus that utilize a reference clock to generate a clock signal and programmable logic devices with combinational logic, phase generators, and flip-flops to create low skew phase enable signals, allowing efficient multiplexing of signals across limited global low skew lines by using a phase generator with internal counters and AND/NAND gates to control signal transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If time domain multiplexing is used to reduce the number of I/O signals across FPGA partitions, then the bandwidth utilization is improved, but the skew between phase enable signals increases due to limited global low skew lines
Solution Approach 1:
The patent introduces an intermediary clock buffer stage between the global low skew clock line and the phase enable signal outputs. This buffer acts as a mediator that receives the clock signal and distributes it to multiple phase enable signal generators, isolating the skew introduced by long interconnect lines from directly affecting the phase enable signals. The buffer refreshes the clock signal locally, reducing the cumulative skew effect while still enabling time domain multiplexing functionality.
Solution Approach 2:
The patent segments the clock distribution function by separating the global clock line from the local phase enable signal generation. Instead of having a single long interconnect carry the clock signal directly to all phase outputs, the system divides the distribution into a global stage (clock line to buffer) and local stages (buffer to individual phase enable signals). This segmentation reduces the skew impact on each segment while maintaining overall system functionality.
2Adaptability or versatility
If the number of fanout loads on phase enable signals is increased to drive more multiplexed signals, then the multiplexing capacity is improved, but the skew between phase enable signals worsens
Solution Approach 1:
The clock buffer serves as an intermediary that can drive multiple fanout loads without proportionally increasing skew. By placing the buffer close to the phase enable signal generators, the system can support more multiplexed signals (higher fanout) while the buffer refreshes the clock signal locally, preventing skew from increasing linearly with the number of loads.
Solution Approach 2:
The patent applies local quality by placing clock buffers at strategic locations close to the phase enable signal generators. This local refresh of the clock signal ensures that even as the number of fanout loads increases, the skew remains controlled in the critical local region where phase enable signals are generated, while the global clock line can support more loads without degrading overall performance.
Data Source
AI summary
An apparatus and method is described for low skew phase generation for multiplexing signals using limited global low skew lines on a multiple FPGA system. The apparatus includes a reference clock programmed to generate a clock signal and programmable logic devices. The programmable logic devices include I/O terminals, combinational logic coupled to the I/O terminals, programmable logic coupled to the combinational logic, a phase generator programmed to receive the clock signal from the reference clock and to generate a phase clock based on the clock signal and a plurality of phase enable signals based on the phase clock, low skew lines to distribute the phase enables with minimal skew caused by routing delays, and flip-flops programmed to have a clock input driven by the phase clock, a data input coupled to ground, and a data output coupled to the combinational logic. Furthermore, synchronous preset inputs of the flip-flops receive the low skew phase enable signals to control transmission design signals by one of the I/O terminal.