Low-Speed Ring Jitter Control for EMI Reduction

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Solution Overview

Problem

Existing electronic systems face challenges in reducing frequency-specific noise and electromagnetic interference (EMI) due to narrow, high amplitude power spectral density (PSD) spikes, particularly in compact, mixed-signal systems.

Innovation Solution

The introduction of a controllable delay device that applies predetermined temporal offsets to digital signals, effectively creating a jittered bit stream to broaden the frequency noise distribution and reduce PSD spikes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Object-affected harmful factors

If conventional EMI suppression techniques (resistors, capacitors, ferrite cores) are used, then electromagnetic interference is reduced, but the solution is not available for high current applications or when SNR is important

Engineering Contradiction:
ImproveEMIVSAvoidapplicability to high current applications
Core Design Contradiction:
Object-affected harmful factorsVSAdaptability or versatility

Solution Approach 1:

The patent replaces conventional physical EMI suppression components (resistors, capacitors, ferrite cores) with a digital signal processing approach. A controllable delay device introduces predetermined temporal offsets to digital signals, converting the EMI suppression mechanism from a physical/circuit-based system to a digital/control-based system. This substitution enables the technique to work in high current applications where conventional components are ineffective or inappropriate.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

2Object-affected harmful factors

If physical EMI suppression components are added to circuits, then EMI is reduced, but device complexity increases

Engineering Contradiction:
ImproveEMIVSAvoidcircuit complexity
Core Design Contradiction:
Object-affected harmful factorsVSDevice complexity

Solution Approach 1:

The patent extracts the EMI suppression function from the physical circuit layer and relocates it to the digital signal processing layer. Instead of adding physical components (resistors, capacitors, ferrite beads) to the circuit, the solution uses a controllable delay device that processes digital signals. This extraction eliminates the need for additional physical components and simplifies the overall device complexity while maintaining EMI suppression effectiveness.

Inventive Principle:
Principle #2Taking out (Extraction)

3Productivity

If digital signals are transmitted at high speed, then data transmission efficiency is improved, but narrow high amplitude PSD spikes occur reducing SNR

Engineering Contradiction:
Improvedata transmission efficiencyVSAvoidsignal to noise ratio
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent introduces dynamic temporal offsets to digital signals using a controllable delay device. The delay amounts are predetermined and can be adjusted, creating dynamic variations in signal timing. This dynamic approach transforms the static, fixed-time digital signals into jittered signals with spread-out spectral content, converting narrow high-amplitude PSD spikes into broader lower-amplitude distributions, thereby improving SNR while maintaining high-speed transmission capability.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS20250150311A1Low-Speed Ring with Controlled Jitter
Publication Date: 2025.05.08 WAYMO LLC
  • US20250150311A1 patent drawing
  • US20250150311A1 patent drawing
  • US20250150311A1 patent drawing

AI summary

Example embodiments relate to communication links, computing systems, and methods for their use. An example embodiment includes a communication link. The communication link includes a low-voltage differential signaling (LVDS) driver. The LVDS driver is configured to provide a differential signal that is based on a digital bit stream. The digital bit stream includes a series of digital bits that are temporally arranged based on a nominal bit period. The communication link also includes a controllable delay device. The controllable delay device is configured to provide a delay signal to the LVDS driver so as to cause a rising edge or a falling edge of respective digital bits to vary in time with respect to the nominal bit period based on a predetermined sequence of delay amounts. The delay amounts represent positive and negative differences in time from the nominal bit period.