Low-Stress Ashable Hardmask Structure for Sub-100 nm Pattern Accuracy
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Solution Overview
Problem
Wiggling of patterned features/lines in semiconductor structures is undesired, especially at sub-100 nm scale, necessitating a solution to achieve precise and accurate feature/line patterns.
Innovation Solution
A hardmask structure comprising a first ashable hardmask with stress from about −100 MPa to about 100 MPa, a first dielectric antireflective coating, and a second ashable hardmask, which reduces deformation and wiggling issues by controlling internal stress, allowing for precise pattern transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional hardmask structures are used for pattern transfer, then manufacturing process can proceed, but wiggling of patterned features occurs especially at sub-100 nm scale
Solution Approach 1:
The patent applies parameter changes by controlling the stress of the bottom ashable hardmask to be within a specific range (−100 MPa to 100 MPa). This stress parameter control prevents deformation of the hardmask during etching, thereby eliminating wiggling of the patterned features and improving pattern accuracy at sub-100 nm scale.
Solution Approach 2:
The patent implements local quality by differentiating the stress requirements for different layers in the hardmask structure. Specifically, the bottom ashable hardmask adjacent to the target layer is controlled to have low stress (−100 MPa to 100 MPa), while no such restriction is imposed on the top ashable hardmask. This localized stress control addresses the wiggling issue at the critical interface without unnecessarily constraining other parts of the structure.
2Ease of manufacture
If hardmask stress is not controlled, then hardmask formation is simpler, but deformation of hardmask occurs during etching process
Solution Approach 1:
The patent introduces a specific stress parameter range (−100 MPa to 100 MPa) for the bottom ashable hardmask as a manufacturing constraint. By controlling this physical parameter during hardmask formation, the patent prevents deformation during subsequent etching while maintaining ease of manufacture through standard deposition and stress control techniques.
3Quantity of substance
If feature size is reduced to sub-100 nm scale, then device density increases, but wiggling of patterned features becomes more severe
Solution Approach 1:
The patent addresses the scaling challenge by implementing stress control (−100 MPa to 100 MPa) on the bottom ashable hardmask. This parameter control ensures that even at sub-100 nm feature sizes where wiggling is naturally more severe, the pattern accuracy is maintained by preventing hardmask deformation during the etching process.
Data Source
AI summary
A hardmask structure and a method of forming a semiconductor structure are provided. The hardmask structure includes a first ashable hardmask, a first dielectric antireflective coating, and a second ashable hardmask. The first dielectric antireflective coating is disposed on the first ashable hardmask. The second ashable hardmask is disposed on the first dielectric antireflective coating. A stress of the first ashable hardmask is from about −100 MPa to about 100 MPa.