Low Supply Active Current Mirror Circuit Design
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Solution Overview
Problem
Existing current mirror circuits are inadequate for quickly settling bias currents within a 40 ns clock cycle, especially when the input device is a 1 uA diode connected input device and the output device requires up to 200 uA, due to minimal headroom and slow response times.
Innovation Solution
The design incorporates a current mirror circuit with five transistors, including a common source amplifier and a bias transistor, along with a switching device for dynamic switching, allowing a small current reference to be mirrored to a large bias current, and includes a static reference device and a gate switch for rapid switching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a prior current mirror circuit is used to mirror current from a 1 uA input device to a 200 uA output device, then the current mirroring function is achieved, but the settling time exceeds the 40 ns clock cycle requirement
Solution Approach 1:
The patent introduces an intermediary current amplifier stage between the input and output devices. This amplifier acts as a mediator that boosts the small input current to a larger intermediate current, which then drives the output device. This intermediate amplification stage enables the output to reach its target current level faster, achieving settling within the 40 ns clock cycle while maintaining accurate current mirroring through the coupled gates of the input and output devices.
2Device complexity
If the output device is directly driven by the input device, then the circuit complexity is low, but the headroom is minimal and response time is slow
Solution Approach 1:
The patent segments the current mirroring function into distinct stages: an input device stage, an intermediate current amplifier stage, and an output device stage. This segmentation allows each stage to be optimized independently - the input device maintains accurate current reference, the amplifier provides current boosting capability for faster response, and the output device delivers the required 200 uA. The segmented architecture improves response time while keeping each individual stage relatively simple.
3Speed
If a current amplifier is added to boost drive current, then the settling speed improves, but the headroom requirement increases
Solution Approach 1:
The patent utilizes the gate voltage dimension to solve the headroom constraint. By coupling the gates of the input device and output device directly, the gate voltage established by the small input current is replicated at the output device gate. This allows the output device to be driven into conduction through voltage control rather than requiring large voltage drops across intermediate components, thereby achieving fast settling speed while minimizing headroom requirements in the voltage domain.
Data Source
AI summary
A circuit can have a low mirror input voltage and fast settling while providing a large current mirror gain. The circuit can include a current source, a first current mirror device having a first transistor and a second transistor and electrically coupled with the current source, a third transistor electrically coupled with the first transistor, a second current mirror device having a fourth transistor and a fifth transistor and electrically coupled between the third transistor and the second transistor, and an output device electrically coupled with the first and second current mirror devices.