Low-Swing Bit-Line Clipper and Split Gate for Memory Energy Efficiency
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Solution Overview
Problem
Current microprocessor and SoC designs face challenges in reducing energy consumption due to limitations in memory array VMIN and dynamic power, which hinder improved energy efficiency.
Innovation Solution
The implementation of a low-swing bit-line operation with clipper devices and split NAND/NOR gate logic for keeper control, reducing switching dynamic capacitance and enabling lower VMIN while maintaining noise tolerance and mitigating keeper aging.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If full swing bit-line operation is used, then noise tolerance is improved, but energy consumption increases
Solution Approach 1:
The bit-line operation is segmented into two phases: precharge phase where bit-lines are charged to full voltage for noise tolerance, and read phase where clipper devices limit the voltage swing to reduce energy consumption. This segmentation allows the system to enjoy the benefits of both full swing and low swing operations at different times.
Solution Approach 2:
The bit-lines are precharged to full voltage levels before the actual read operation. This preliminary action ensures that the bit-lines have sufficient voltage headroom to tolerate noise during sensing, while the clipper devices subsequently limit the energy-consuming voltage swing during the read phase.
2Use of energy by moving object
If minimum operating voltage VMIN is lowered to improve energy efficiency, then dynamic power consumption decreases, but memory data retention becomes unreliable
Solution Approach 1:
The patent changes the voltage parameter dynamically by using clipper devices to limit the bit-line voltage swing to a reduced level (Vdd - Vt) during read operations. This parameter change allows the memory to operate reliably at lower supply voltages while maintaining sufficient noise margin and data retention through the precharge phase.
Solution Approach 2:
The system dynamically adjusts the bit-line voltage characteristics through clipper devices that activate during read operations to limit voltage swing, while allowing full voltage operation during precharge. This dynamic behavior enables the memory to maintain reliability across different operating conditions while reducing average power consumption.
3Reliability
If keeper circuit operation is enhanced to improve data retention, then reliability improves, but keeper aging increases
Solution Approach 1:
The clipper devices provide partial voltage swing limitation during read operations, which is sufficient to reduce energy consumption and mitigate keeper aging, while the precharge phase provides excessive voltage headroom to ensure reliable data retention. This partial action approach balances reliability requirements with aging mitigation.
Data Source
AI summary
Described is an apparatus which comprises: a bit-line (BL) read port; a first local bit-line (LBL) coupled to the BL read port; a second LBL; and one or more clipper devices coupled to the first and second LBLs. The apparatus allows for low swing bit-line to be used for large signal memory arrays. The low swing operation enables reduction in switching dynamic capacitance. The apparatus also describes a split input NAND/NOR gate for bit-line keeper control which achieves lower VMIN, higher noise tolerance, and improved keeper aging mitigation. Described is also an apparatus for low swing write operation which can be enabled at high voltage without degrading the low voltage operation.