Low-Swing Buffer Circuit for Clock Power Reduction
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Solution Overview
Problem
Integrated circuits face significant power consumption challenges in signal distribution, particularly in clock distribution networks, where power supply voltage levels have not decreased commensurate with increasing computing demands, leading to substantial power dissipation and impacting mobile device performance and cost.
Innovation Solution
Implementing a low-swing clock distribution network using low-power buffers that reduce voltage swing, achieved through swing-limiting circuits and control signals, allowing for reduced dynamic and static power consumption without additional power supplies, and maintaining buffer size comparable to standard CMOS buffers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If standard inverter-based buffers are used for signal distribution, then full voltage swing is achieved, but power consumption increases substantially
Solution Approach 1:
The patent changes the voltage swing parameter from full swing (VDD to GND) to reduced swing (VDD to an intermediate voltage level). This is achieved by modifying the pull-up circuit to use a current source that limits the maximum voltage reached at the output node, thereby reducing dynamic power consumption proportionally to the square of the voltage swing reduction.
2Loss of energy
If voltage swing is reduced to lower power consumption, then dynamic power is reduced, but signal driving capability may be compromised
Solution Approach 1:
The patent implements dynamic control of the output stage by using a control signal that enables strong pull-up and pull-down circuits only during transition periods. During steady states, weak pull-up circuits maintain the reduced voltage level with minimal power consumption. This dynamic switching allows the circuit to provide full driving capability when needed while consuming minimal power during stable operation.
Solution Approach 2:
The patent employs periodic activation of strong drive circuits synchronized with the clock signal transitions. The strong pull-up and pull-down circuits are activated only during the brief transition periods when voltage changes are needed, while weak pull-up circuits handle steady-state maintenance. This periodic action pattern reduces overall power dissipation while maintaining signal integrity during critical transition phases.
3Loss of energy
If additional power supply nodes are added to enable low-swing operation, then power consumption is reduced, but device complexity increases
Solution Approach 1:
The patent makes the existing VDD power supply node multi-functional by using it both as the full-swing reference and as the basis for reduced-swing operation. The current source-based pull-up circuit draws from the same VDD node but limits current to achieve reduced voltage swing, eliminating the need for separate intermediate voltage power supplies while still achieving power reduction goals.
Data Source
AI summary
An apparatus includes a first circuit of a first type that couples an output node to a first power supply node in response to a first value of a control signal. The apparatus includes a second circuit of a second type to couple the output node to the first power supply node in response to a first value of a first signal having a first voltage swing. The apparatus includes a third circuit of the second type to couple the output node to a second power supply node in response to a second value of the first signal. The apparatus includes a control circuit that generates the control signal based on the first signal and an output signal on the output node. The first, second, and third circuits generate an output signal on the output node. The output signal has a second voltage swing less than the first voltage swing.