Low-Swing Clock Sequential Circuits With Full-Range Output
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Solution Overview
Problem
Digital integrated circuits face challenges in managing clock signal distribution due to high clock frequencies, leading to increased clock skew and jitter, which results in significant power consumption, with clock power often accounting for 50% or more of the overall power consumption.
Innovation Solution
The implementation of low voltage clock swing sequential circuits using transistor stacks with specific coupling configurations allows the clock signal to swing to the full voltage range even when the clock logic high level is below the supply voltage, reducing power consumption by minimizing voltage swing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the clock signal swings to the full voltage range, then the sequential circuit can operate reliably, but the power consumption increases significantly
Solution Approach 1:
The patent changes the voltage parameter of the clock signal from full swing (0 to VDD) to reduced swing (0 to a fraction of VDD, e.g., 0.2V to 0.8V). This parameter change allows the sequential circuit to operate reliably with much lower power consumption, as power is proportional to voltage squared. The enabling P-type transistors ensure full voltage range at the output despite the reduced clock swing.
2Use of energy by moving object
If the clock logic high level is reduced below the supply voltage, then power consumption decreases, but the output data signal cannot reach the full voltage range
Solution Approach 1:
The enabling P-type transistors act as intermediary elements that couple the clock signal to the pull-up network. These transistors are controlled by the clock signal and enable the output to reach full VDD through the pull-up transistors even when the clock high level is reduced. This intermediary mechanism allows decoupling of the clock voltage level from the output voltage level.
3Reliability
If a complex clock tree is used to distribute clock signals, then clock skew and jitter are controlled, but the power consumption and device complexity increase
Solution Approach 1:
The patent changes the voltage swing parameter of the clock signal to reduce power consumption in the clock tree. By operating with reduced voltage swing, the clock tree consumes less power and can be simpler in structure, while the sequential elements still receive adequate clocking signals for reliable operation.
4Reliability
If a complex clock tree is used to distribute clock signals, then clock skew and jitter are controlled, but the power consumption increases
Solution Approach 1:
The patent changes the voltage swing parameter of the clock signal from full range to reduced range (e.g., 0.2V to 0.8V instead of 0 to VDD). This parameter change directly reduces the power consumption of the clock tree while maintaining adequate clocking functionality. The reduced voltage swing decreases dynamic power consumption proportionally to the square of the voltage reduction.
Data Source
AI summary
Systems, apparatuses, and methods for implementing low voltage clock swing sequential circuits are described. An input signal is coupled to the gates of a first P-type transistor and a first N-type transistor of a first transistor stack. A low voltage swing clock signal is coupled to the gate of a second N-type transistor of the first transistor stack. An inverse of the input signal is coupled to the gates of a second P-type transistor and a third N-type transistor of a second transistor stack. The low-swing clock is coupled to the gate of a fourth N-type transistor of the second transistor stack. A first end of one or more enabling P-Type transistors with gates coupled to the low-swing clock is coupled to the first P-type transistor's drain, and a second end of the one or more enabling P-Type transistors is coupled to the second P-type transistor's drain.