Low-Swing Clock Distribution for Phase Interpolator Linearity
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Solution Overview
Problem
The operating speed of peripheral devices such as memories, communication devices, and graphic devices has not kept up with the speed of processors, leading to a significant speed difference, and existing phase interpolators suffer from nonlinearity and increased jitter due to inappropriate common mode levels of clock signals.
Innovation Solution
A clock signal distribution circuit using NMOS-based regulators and drivers to output low swing clock signals, which are then processed by a PMOS-based input buffer to improve linearity, reliability, and accuracy, while reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a common mode level of clock signals is not controlled appropriately in CML-based phase interpolator, then the circuit operation is simple, but nonlinearity occurs in output and jitter increases
Solution Approach 1:
The patent applies preliminary action by controlling the common mode level of clock signals before they are input to the phase interpolator. The clock signal control circuit adjusts the voltage levels of input clock signals in advance, ensuring they meet the required common mode level range, which prevents nonlinearity and jitter in the phase interpolator output without adding complexity to the phase interpolator itself.
Solution Approach 2:
The patent uses an intermediary approach by introducing a separate clock signal control circuit as a mediator between the clock signal source and the phase interpolator. This intermediary circuit adjusts the clock signal parameters (common mode level) to be suitable for the phase interpolator, isolating the phase interpolator from direct control complexity while ensuring optimal input conditions.
2Use of energy by moving object
If the clock signal voltage level is not regulated, then the power consumption is higher, but the signal strength is sufficient
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting the voltage level parameter of clock signals through the clock signal control circuit. The circuit regulates the common mode level of input clock signals to optimal values, which reduces power consumption in the phase interpolator while maintaining sufficient signal strength for proper operation. This is achieved by changing the voltage parameter to match the specific requirements of the phase interpolator circuit.
Data Source
AI summary
A clock signal distribution circuit includes an n-type metal-oxide semiconductor (NMOS)-based regulator configured to receive a first voltage and output a regulator voltage having a lower voltage level than the first voltage through a regulator voltage output node, and an NMOS-based driver including a first sub-driver configured to include first to fourth NMOS transistors and receive first and second clock signals and output first and second low swing clock signals.