Low-Temperature 3D Memory Fabrication via Resistive Switching
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Solution Overview
Problem
Current semiconductor memory devices face challenges such as short channel effects, high programming voltage leading to dielectric breakdown, and compatibility issues with CMOS manufacturing as they scale to smaller sizes, particularly with non-volatile memory devices like Flash, Fe-RAM, MRAM, and ORAM, which require new materials and suffer from performance degradations.
Innovation Solution
A method and device structure for forming a vertically stacked non-volatile memory device using a p-n junction region with a resistive switching material and a steering device, fabricated at low temperatures (no greater than 450°C) compatible with CMOS processes, utilizing materials like doped zinc oxide and polycrystalline silicon germanium for enhanced scalability and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If new materials are used for next generation non-volatile memory devices (Fe-RAM, MRAM, ORAM, PCRAM), then non-volatile memory functionality is achieved, but compatibility with CMOS manufacturing is lost due to high temperature anneal requirements and incompatible materials
Solution Approach 1:
The patent changes the temperature parameter from high temperature (required by conventional Fe-RAM, MRAM, PCRAM) to low temperature (≤450°C), enabling CMOS compatibility while maintaining non-volatile memory functionality through resistive switching mechanisms in metal oxide materials
Solution Approach 2:
The patent uses composite material structures including metal oxide resistive switching materials combined with doped polysilicon steering devices, creating a hybrid structure that achieves non-volatile memory functionality while being compatible with CMOS manufacturing processes
2Productivity
If device sizes are scaled down to overcome short channel effects and improve density, then device density is increased, but performance degradation occurs due to high programming voltage causing dielectric breakdown
Solution Approach 1:
The patent replaces the mechanical/electrical field effect transistor switching mechanism with a resistive switching mechanism in metal oxide materials, which does not require high programming voltages and avoids dielectric breakdown issues when scaling to smaller dimensions
Solution Approach 2:
The patent transitions from planar 2D memory structures to vertically stacked 3D structures, increasing device density while maintaining reliable operation at scaled dimensions by utilizing the vertical dimension for multiple memory cell stacking
3Reliability
If high temperature anneal steps are used for Fe-RAM and MRAM fabrication, then material crystallization and device performance are improved, but integration with large volume silicon-based fabrication techniques is prevented
Solution Approach 1:
The patent changes the thermal processing parameter from high temperature anneal to low temperature processing (≤450°C), enabling integration with standard CMOS fabrication lines while achieving sufficient material crystallization and device performance through alternative processing methods
4Reliability
If PCRAM devices use Joules heating for switching, then phase change memory functionality is achieved, but power consumption increases undesirably
Solution Approach 1:
The patent replaces the Joules heating-based phase change mechanism with an electric field-driven resistive switching mechanism in metal oxide materials, significantly reducing power consumption while maintaining non-volatile memory functionality
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables the formation of high-density memory devices with improved scalability and reduced power consumption, maintaining reliability and compatibility with CMOS manufacturing, while reducing the need for high-temperature anneal steps and incompatible materials.
Implementation Method 1
a resistive switching material having an n type semiconductor impurity characteristic is formed overlying the first p type semiconductor material
Implementation Method 2
A method and device structure for forming a vertically stacked non-volatile memory device using a p-n junction region with a resistive switching material and a steering device
Data Source
AI summary
A non-volatile memory device structure. The device structure includes a first electrode, a second electrode and a state change material sandwiched between the first electrode and the second electrode. In a specific embodiment, the first electrode includes a p+ type polycrystalline silicon material or a p+ type silicon germanium material. The state change material includes an n− type zinc oxide material. The second electrode includes a doped zinc oxide material. The doped zinc oxide material can be B2O3:ZnO, In2O3:ZnO, Al2O3:ZnO or Ga2O3:ZnO. The n− type zinc oxide material and the p+ type silicon material (or p+ polycrystalline silicon germanium material) further form a diode device or steering device for the non-volatile memory device.