Low-Temperature Bonding of 3D Heterostructures

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Solution Overview

Problem

Existing low-temperature bonding processes for substrates or wafers often result in defects at the bonding interface, which adversely affect the bonding energy, making it challenging to achieve high-quality bonding without high-temperature heat treatment, especially when components or circuits are present.

Innovation Solution

A method involving the formation of bonding layers on substrates at low temperatures, followed by a degassing annealing to remove contaminants, and subsequent molecular adhesion with a bonding interface strengthening annealing at temperatures below 450°C, ensuring a gradual or rapid temperature ramp to maintain bonding energy and prevent defects.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Temperature

If low-temperature bonding is used to avoid damage to components or circuits, then the substrates can be assembled without high-temperature heat treatment, but defects appear at the bonding interface and bonding energy is reduced

Engineering Contradiction:
Improvebonding temperatureVSAvoidbonding interface quality
Core Design Contradiction:
TemperatureVSReliability

Solution Approach 1:

The bonding layers are pre-annealed at low temperatures (below 450°C) before the actual bonding process. This preliminary action removes contaminants and prepares the bonding surfaces, enabling high-quality bonding at low temperatures without damaging components or circuits while avoiding interface defects

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent changes the temperature parameters of the annealing process, specifically using low temperatures (below 450°C) that are sufficient to activate the bonding layers and remove contaminants but low enough to prevent damage to temperature-sensitive components and circuits on the substrates

Inventive Principle:
Principle #35Parameter changes

2Temperature

If low-temperature bonding layers are formed to protect components, then substrates can be assembled at low temperatures, but bonding energy is insufficient and interface defects occur

Engineering Contradiction:
Improvebonding layer formation temperatureVSAvoidbonding energy
Core Design Contradiction:
TemperatureVSStrength

Solution Approach 1:

A preliminary annealing step is performed on the bonding layers at low temperatures (below 450°C) before bonding. This activates the bonding layers and removes contaminants, enabling strong bonding (≥3 J/m²) at low temperatures without damaging components

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The bonding layers are formed and then immediately annealed in a continuous low-temperature process, maintaining the beneficial low-temperature condition throughout while achieving both strong bonding and component protection

Inventive Principle:
Principle #20Continuity of useful action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This method achieves high bonding energies of at least 3 J/m2 with minimal defects, enabling the assembly of substrates or wafers with components or circuits without high-temperature treatments, thus overcoming the limitations of prior low-temperature bonding processes.

Implementation Method 1

conducting a first annealing of the first and second bonding layers on the first and second substrates for a first annealing time period

Methodology Applied
Scientific EffectAnnealing: Annealing

Implementation Method 2

The first annealing of the first and second bonding layers at a temperature below 450° C. removes contaminants from the bonding layers

Methodology Applied
Scientific EffectThermal desorption: Desorption

Implementation Method 3

contacting the exposed surfaces of the first bonding layer and the second bonding layer produces bonding by molecular adhesion

Methodology Applied
Scientific EffectMolecular adhesion: Van der Waals Force

Data Source

PatentUS9117686B23D integrated heterostructures having low-temperature bonded interfaces with high bonding energy
Publication Date: 2015.08.25 SOITEC SA
  • US9117686B2 patent drawing
  • US9117686B2 patent drawing
  • US9117686B2 patent drawing

AI summary

The invention relates to a process for assembling a first element that includes at least one first wafer, substrate or at least one chip, and a second element of at least one second wafer or substrate, involving the formation of a surface layer, known as a bonding layer, on each substrate, at least one of the bonding layers being formed at a temperature less than or equal to 300° C.; conducting a first annealing, known as degassing annealing, of the bonding layers, before assembly, at least partly at a temperature at least equal to the subsequent bonding interface strengthening temperature but below 450° C.; forming an assembling of the substrates by bringing into contact the exposed surfaces of the bonding layers, and conducting an annealing of the assembled structure at a bonding interface strengthening temperature below 450° C.