Low-Temperature Ion Implantation for Floating Gate Conductivity
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Solution Overview
Problem
The floating gate in flash memory devices experiences dopant loss during high-temperature processes, leading to reduced conductivity and reliability issues.
Innovation Solution
A low-temperature implantation process is used to compensate for dopant loss, with a process temperature no more than -50°C and the same conductivity type dopant being implanted into doped semiconductor patterns, optionally using a tilted ion implantation process and screen layers to minimize damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-temperature processes are used to form the floating gate, then the doping process is effective, but dopant loss occurs leading to reduced conductivity
Solution Approach 1:
The patent changes the temperature parameter of the implantation process from conventional high temperature to low temperature (no more than -50°C). This parameter change prevents dopant loss while maintaining effective doping, as the low temperature reduces dopant diffusion and loss during the implantation process, thereby maintaining the required conductivity of the floating gate
2Loss of substance
If low-temperature implantation is used to compensate dopant loss, then dopant loss is reduced, but the implantation process becomes more complex
Solution Approach 1:
The patent applies preliminary action by performing the low-temperature implantation process early in the fabrication sequence, before subsequent high-temperature processes that would cause dopant loss. The implantation is conducted at low temperature first to establish the dopant profile, and then other processes are performed afterward, preventing dopant loss without requiring complex process modifications
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Maintains the required conductivity of the floating gate, improving the performance and reliability of the semiconductor device by preventing dopant loss and deformation.
Implementation Method 1
An implantation process is performed to implant a dopant into the first doped semiconductor patterns, wherein a process temperature of the implantation process is no more than about −50° C.
Implementation Method 2
the dopant loss of the floating gate occurs during the high-temperature subsequent processes. As a result, the conductivity of the floating gate is reduced
Implementation Method 3
the implantation process comprises a tilted ion implantation process. the tilted ion implantation process is performed with a tilt angle of about 20° to 60°
Data Source
AI summary
The method for fabricating a semiconductor device is provided. A doped semiconductor layer is formed over the substrate. The doped semiconductor layer is patterned to form a plurality of doped semiconductor patterns. An implantation process is performed to implant a dopant into the doped semiconductor patterns. A process temperature of the implantation process is no more than about −50° C. The dopants of the implantation process and the doped semiconductor patterns have the same conductivity type.