Low-Temperature Selective Epitaxy for Backside Contact Formation
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Solution Overview
Problem
Current selective epitaxial deposition processes face challenges in achieving selective epitaxial deposition at low temperatures (e.g., 500 degrees Celsius or less) due to thermal budget limitations and the inefficiency of etching gases like hydrogen chloride, which complicates the formation of backside power delivery networks in semiconductor devices.
Innovation Solution
The method involves epitaxially growing doped crystalline and amorphous silicon-containing layers at temperatures below 500 degrees Celsius using higher order silane and chlorosilane precursors, along with n-type dopant precursors, and selectively removing the amorphous layers relative to the crystalline capping layer using etching gases like Cl2, GeCl2, or GeCl4, without breaking vacuum, to form backside power rails.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If typical selective epitaxial deposition processes are used, then epitaxial layers can be formed on monocrystalline surfaces, but the process requires high temperatures (above 500 degrees Celsius) that exceed the thermal budget of the semiconductor device
Solution Approach 1:
The patent changes the chemical parameters of the deposition process by using alternative precursor gases (such as silane-based precursors instead of traditional silicon tetrachloride) and modifies the etching chemistry to enable selective epitaxial growth at temperatures of 500 degrees Celsius or below, thereby complying with the device's thermal budget while maintaining deposition functionality
Solution Approach 2:
The process employs composite gas phase reactions combining multiple chemical components (precursor gases, carrier gases, and etching gases) that work synergistically to enable low-temperature selective epitaxial deposition, where the composite chemical environment facilitates both deposition and selective removal at reduced temperatures
2Temperature
If conventional etching gases like hydrogen chloride are used at low temperatures, then the epitaxial deposition can proceed at lower temperatures, but the etching selectivity between epitaxial layers and polycrystalline/amorphous layers becomes insufficient
Solution Approach 1:
The patent modifies the etching gas composition and process parameters to achieve adequate etching selectivity at low temperatures, using alternative gas chemistries that maintain differential etching rates between crystalline and non-crystalline silicon layers despite the reduced thermal energy available for etching reactions
3Manufacturing precision
If cyclic deposition/etch processes are implemented to achieve selectivity, then some selective removal can be achieved, but the process becomes complex, difficult to maintain, and has low throughput
Solution Approach 1:
The patent combines the deposition and etching functions into a single integrated process step by using precursor gases that simultaneously enable epitaxial growth on monocrystalline surfaces while being selectively removed from polycrystalline and amorphous surfaces, thereby eliminating the need for separate cyclic deposition and etching operations and simplifying the overall manufacturing process
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables low-temperature selective epitaxial deposition suitable for logic backside contact and other applications, allowing for the formation of backside power delivery networks with high active dopant concentration and improved manufacturing efficiency.
Implementation Method 1
epitaxially growing a doped crystalline silicon-containing layer over a source/drain feature
Implementation Method 2
epitaxially growing a doped crystalline silicon-containing layer over a source/drain feature and growing a doped amorphous silicon-containing layer over a field region
Implementation Method 3
selectively removing the doped amorphous silicon-containing layer and the undoped amorphous silicon-containing layer relative to the silicon-containing crystalline capping layer
Data Source
AI summary
Semiconductor devices and methods for manufacturing the same are provided. The method includes epitaxially growing a doped crystalline silicon-containing layer over a source/drain feature and growing a doped amorphous silicon-containing layer over a field region of a semiconductor layer. The trench is formed in the semiconductor layer and the trench exposes the source/drain feature. The method further includes epitaxially growing an undoped crystalline silicon-containing capping layer over the doped crystalline silicon-containing layer and growing an undoped amorphous silicon-containing layer over the doped silicon-containing amorphous layer. The method further includes selectively removing the doped amorphous silicon-containing layer and the undoped amorphous silicon-containing layer relative to the silicon-containing crystalline capping layer. The method further includes removing the silicon-containing crystalline capping layer to expose the doped silicon-containing crystalline layer.