Low Temperature Silicon Conductor for CMOS Memory
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Solution Overview
Problem
Current resistive-switching memory technologies face challenges in compatibility with CMOS fabrication processes, particularly due to temperature constraints and material incompatibilities, leading to increased fabrication costs and complexity.
Innovation Solution
The development of two-terminal memory cells using silicon-based conductors doped at low temperatures, allowing for continuous deposition processes without intervening interface layers, which are compatible with existing CMOS fabrication techniques and reduce overhead costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high temperature doping processes are used to achieve proper conductivity in silicon-based conductors, then the electrical properties are improved, but compatibility with CMOS fabrication processes deteriorates due to temperature constraints
Solution Approach 1:
The patent applies parameter changes by modifying the doping temperature from conventional high temperatures (typically >700°C) to low temperatures (below 450°C). This is achieved through specific doping techniques and material composition adjustments that enable adequate electrical conductivity at reduced temperatures, thereby resolving the contradiction between achieving proper electrical properties and maintaining CMOS process compatibility.
2Reliability
If multiple interface layers are introduced between silicon-based layers, then material compatibility and interface quality are improved, but fabrication complexity and overhead costs increase
Solution Approach 1:
The patent merges adjacent silicon-based layers directly without introducing intervening interface layers. This consolidation approach maintains adequate interface quality through direct silicon-silicon bonding while significantly reducing fabrication complexity and eliminating the need for additional processing steps associated with depositing and patterning separate interface layers.
Solution Approach 2:
The patent extracts and eliminates the intervening interface layers from the structure between silicon-based conductor layers. By removing these intermediate layers, the invention simplifies the overall device architecture and fabrication process while maintaining the necessary electrical and structural properties through direct silicon layer contact.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the fabrication of resistive-switching memory cells at lower temperatures, reducing fabrication complexity and costs, while maintaining compatibility with CMOS processes, thus improving the efficiency and scalability of memory cell production.
Implementation Method 1
The silicon based conductor material can be doped to provide a target resistivity
Implementation Method 2
the conductor material can be doped at a temperature less than 450 degrees Celsius, facilitating compatibility with many CMOS-related fabrication processes
Data Source
AI summary
Providing for two-terminal memory cell structures and fabrication that can be achieved with a relatively low temperature process(es) is described herein. By way of example, disclosed two-terminal memory cells can be formed at least in part as a continuous deposition, potentially yielding improved efficiency in manufacturing. Furthermore, various embodiments can be compatible with some existing complementary metal oxide semiconductor fabrication processes, reducing or avoiding retooling overhead that might be associated with modifying existing fabrication processes in favor of other two-terminal memory cell fabrication techniques.