Low-Temperature N-Type Silicon Epitaxy With Selective Amorphous Etch
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Solution Overview
Problem
Existing selective epitaxial deposition processes struggle to maintain a suitable selective window between epitaxial and polycrystalline/amorphous layers at lower processing temperatures, leading to complex and low-throughput cyclic deposition/etch processes.
Innovation Solution
A method involving a first deposition process to form an n-type doped semiconductor layer, a second deposition process to form a capping layer with a different n-type dopant, and an etch process to selectively remove amorphous portions, using dopants like arsenic or antimony to block phosphorous diffusion and enhance etch selectivity, all performed at temperatures below 500 degrees Celsius.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If lower processing temperatures (e.g., about 500 degrees Celsius or less) are used in selective epitaxial deposition, then device critical dimensions can be maintained and thermal damage reduced, but typical etching gases fail to provide a suitable selective window between the epitaxial layer and the polycrystalline and/or amorphous layer
Solution Approach 1:
The patent changes the chemical composition parameters of the dopants in the semiconductor layer. By using specific dopant combinations (e.g., phosphorus with arsenic or antimony) at controlled concentrations, the etch selectivity is enhanced without requiring higher processing temperatures. This allows maintaining low temperature processing while achieving the needed selective window for etching.
Solution Approach 2:
The patent creates a composite doped semiconductor layer with multiple dopant types (e.g., phosphorus + arsenic or phosphorus + antimony). This composite doping approach modifies the material properties to achieve both low-temperature compatibility and improved etch selectivity, resolving the contradiction between temperature and selectivity requirements.
2Manufacturing precision
If cyclic deposition/etch processes are used to achieve selective epitaxial deposition, then some selectivity can be obtained, but the processes become complex, difficult to maintain, and have low throughput
Solution Approach 1:
The patent extracts and eliminates the need for complex cyclic deposition/etch sequences by using a single-step selective epitaxial deposition process. By incorporating specific dopant combinations into the semiconductor layer, the process achieves selective deposition without requiring multiple cyclic steps, thereby simplifying the process and improving throughput.
Solution Approach 2:
The patent segments the doping function into specific dopant roles within the semiconductor layer. By using primary dopants (e.g., phosphorus) combined with secondary dopants (e.g., arsenic or antimony), the process achieves both selective deposition and etch resistance in a single step, eliminating the need for segmented cyclic processes.
3Quantity of substance
If higher dopant concentrations are deposited to improve device performance, then electrical characteristics are enhanced, but dopant diffusion into adjacent layers increases, especially at lower processing temperatures
Solution Approach 1:
The patent introduces secondary dopants (arsenic or antimony) as intermediary elements that interact with the primary dopant (phosphorus). These intermediary dopants form complexes or modify the diffusion behavior of phosphorus, thereby controlling dopant diffusion into adjacent layers while maintaining high dopant concentrations in the semiconductor layer.
Solution Approach 2:
The patent uses composite doping with multiple dopant types (phosphorus + arsenic or phosphorus + antimony) to achieve high dopant concentration while controlling diffusion. The interaction between different dopant species in the composite structure modifies diffusion characteristics, allowing high electrical performance without excessive dopant spread into adjacent layers.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method improves throughput and adaptability, enabling high-dopant concentration deposition with enhanced etch selectivity and process window tuning, suitable for advanced semiconductor structures.
Implementation Method 1
The etch process selectively removing an amorphous portion of the n-type doped semiconductor layer and an amorphous portion of the n-type doped capping layer, and leaving an epitaxial portion of the n-type doped semiconductor layer and optionally an epitaxial portion of the n-type doped capping layer
Implementation Method 2
A typical selective epitaxy process involves a deposition reaction and an etch reaction. The deposition reaction causes an epitaxial layer to be formed on monocrystalline surfaces of a substrate
Implementation Method 3
using dopants like arsenic or antimony to block phosphorous diffusion
Data Source
AI summary
Semiconductor devices and methods for manufacturing semiconductor devices that include low temperature selective deposition of epitaxial silicon-containing films are provided. The method includes performing a first deposition process, a second deposition process subsequent to the first deposition process, and an etch process. The first deposition process includes forming an n-type doped semiconductor layer including a first n-type dopant on an exposed surface of a substrate. The second deposition process includes forming an n-type doped capping layer on the doped semiconductor layer, the n-type doped capping layer including a second n-type dopant different from the first n-type dopant. The etch process selectively removing an amorphous portion of the n-type doped semiconductor layer and an amorphous portion of the n-type doped capping layer, and leaving an epitaxial portion of the n-type doped semiconductor layer and an epitaxial portion of the n-type doped capping layer.